公开(公告)号：US20210376094A1

公开(公告)日：2021-12-02

申请号：US17199933

申请日：2021-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Po Lin ,  Wei-Yang Lee ,  Yuan-Ching Peng ,  Chia-Pin Lin ,  Jiun-Ming Kuo

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/40 ,  H01L29/66

Abstract: A method includes depositing a dummy semiconductor layer and a first semiconductor layer over a substrate, forming spacers on sidewalls of the dummy semiconductor layer, forming a first epitaxial material in the substrate, exposing the dummy semiconductor layer and the first epitaxial material, where exposing the dummy semiconductor layer and the first epitaxial material includes thinning a backside of the substrate, etching the dummy semiconductor layer to expose the first semiconductor layer, where the spacers remain over and in contact with end portions of the first semiconductor layer while etching the dummy semiconductor layer, etching portions of the first semiconductor layer using the spacers as a mask, and replacing a second epitaxial material and the first epitaxial material with a backside via, the backside via being electrically coupled to a source/drain region of a first transistor.

公开(公告)号：US11799002B2

公开(公告)日：2023-10-24

申请号：US17199933

申请日：2021-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Po Lin ,  Wei-Yang Lee ,  Yuan-Ching Peng ,  Chia-Pin Lin ,  Jiun-Ming Kuo

IPC: H01L21/768 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78696

Abstract: A method includes depositing a dummy semiconductor layer and a first semiconductor layer over a substrate, forming spacers on sidewalls of the dummy semiconductor layer, forming a first epitaxial material in the substrate, exposing the dummy semiconductor layer and the first epitaxial material, where exposing the dummy semiconductor layer and the first epitaxial material includes thinning a backside of the substrate, etching the dummy semiconductor layer to expose the first semiconductor layer, where the spacers remain over and in contact with end portions of the first semiconductor layer while etching the dummy semiconductor layer, etching portions of the first semiconductor layer using the spacers as a mask, and replacing a second epitaxial material and the first epitaxial material with a backside via, the backside via being electrically coupled to a source/drain region of a first transistor.