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公开(公告)号:US11973122B2
公开(公告)日:2024-04-30
申请号:US17406937
申请日:2021-08-19
发明人: I-Hsieh Wong , Wei-Yang Lee , Chia-Pin Lin
IPC分类号: H01L29/423 , H01L29/06 , H01L29/417 , H01L29/66 , H01L29/786
CPC分类号: H01L29/42392 , H01L29/0665 , H01L29/41775 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/78696
摘要: Embodiments utilize a two layer inner spacer structure during formation of the inner spacers of a nano-FET device. The materials of the first inner spacer layer and second inner spacer layer can be selected to have a mismatch in their coefficients of thermal expansion (CTE). As the structure cools after deposition, the inner spacer layer which has a larger CTE will exhibit compressive stress on the other inner spacer layer, however, because the two layers have a common interface, the layer with the smaller CTE will exhibit a counter acting tensile stress.
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公开(公告)号:US20240128376A1
公开(公告)日:2024-04-18
申请号:US18395892
申请日:2023-12-26
发明人: Shih-Chiang Chen , Wei-Yang Lee , Chia-Pin Lin , Yuan-Ching Peng
IPC分类号: H01L29/78 , H01L21/8234 , H01L27/088 , H01L29/08 , H01L29/423 , H01L29/49 , H01L29/66 , H01L29/786
CPC分类号: H01L29/7851 , H01L21/823418 , H01L21/823431 , H01L27/0886 , H01L29/0847 , H01L29/42392 , H01L29/4991 , H01L29/66795 , H01L29/78696
摘要: A device a includes a substrate, two source/drain (S/D) features over the substrate, and semiconductor layers suspended over the substrate and connecting the two S/D features. The device further includes a dielectric layer disposed between two adjacent layers of the semiconductor layers and an air gap between the dielectric layer and one of the S/D features, where a ratio between a length of the air gap to a thickness of the first dielectric layer is in a range of 0.1 to 1.0.
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公开(公告)号:US11935781B2
公开(公告)日:2024-03-19
申请号:US17815669
申请日:2022-07-28
发明人: Che-Lun Chang , Wei-Yang Lee , Chia-Pin Lin , Yuan-Ching Peng
IPC分类号: H01L21/768 , H01L21/306 , H01L21/762 , H01L23/522 , H01L23/532 , H01L29/06 , H01L29/08 , H01L29/417 , H01L29/423 , H01L29/45 , H01L29/66 , H01L29/786
CPC分类号: H01L21/7682 , H01L21/7624 , H01L21/76804 , H01L21/76805 , H01L23/5226 , H01L23/5329 , H01L29/41733 , H01L29/66439 , H01L29/66742 , H01L21/30604 , H01L29/0673 , H01L29/0847 , H01L29/42392 , H01L29/45 , H01L29/78696
摘要: An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is on a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is on a backside of the source epitaxial structure and a backside of the drain epitaxial structure and has an air gap therein. The backside via extends through the backside dielectric layer to a first one of the source epitaxial structure and the drain epitaxial structure.
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公开(公告)号:US11855220B2
公开(公告)日:2023-12-26
申请号:US17850036
申请日:2022-06-27
发明人: Shih-Chiang Chen , Wei-Yang Lee , Chia-Pin Lin , Yuan-Ching Peng
IPC分类号: H01L29/78 , H01L21/8234 , H01L27/088 , H01L29/66 , H01L29/06 , H01L29/423 , H01L29/49 , H01L21/8238 , H01L27/092 , H01L29/08
CPC分类号: H01L29/7851 , H01L21/823418 , H01L21/823431 , H01L27/0886 , H01L29/0847 , H01L29/66795
摘要: A device a includes a substrate, two source/drain (S/D) features over the substrate, and semiconductor layers suspended over the substrate and connecting the two S/D features. The device further includes a dielectric layer disposed between two adjacent layers of the semiconductor layers and an air gap between the dielectric layer and one of the S/D features, where a ratio between a length of the air gap to a thickness of the first dielectric layer is in a range of 0.1 to 1.0.
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公开(公告)号:US11682714B2
公开(公告)日:2023-06-20
申请号:US17706296
申请日:2022-03-28
发明人: Bone-Fong Wu , Chih-Hao Yu , Chia-Pin Lin
IPC分类号: H01L29/66 , H01L29/06 , H01L29/423 , H01L29/78 , H01L21/02
CPC分类号: H01L29/66553 , H01L29/0653 , H01L29/42392 , H01L29/6653 , H01L29/6656 , H01L29/6681 , H01L29/7853 , H01L21/0214 , H01L21/0228
摘要: A semiconductor device according to the present disclosure includes a channel member including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion, a first inner spacer feature disposed over and in contact with the first connection portion, a second inner spacer feature disposed under and in contact with the first connection portion, and a gate structure wrapping around the channel portion of the channel member. The channel member further includes a first ridge on a top surface of the channel member and disposed at an interface between the channel portion and the first connection portion. The first ridge partially extends between the first inner spacer feature and the gate structure.
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公开(公告)号:US20220367670A1
公开(公告)日:2022-11-17
申请号:US17320428
申请日:2021-05-14
发明人: Wei-Jen Lai , Wei-Yuan Lu , Chia-Pin Lin
IPC分类号: H01L29/66 , H01L29/78 , H01L21/8234
摘要: A method according to the present disclosure includes depositing, over a substrate, a stack including channel layers interleaved by sacrificial layers, forming a first fin structure and a second fin in a first area and a second area of the substrate, depositing a first dummy gate stack over the first fin structure and a second dummy gate stack over the second fin structure, recessing source/drain regions of the first fin structure and second fin structure to form first source/drain trenches and second source/drain trenches, selectively and partially etching the sacrificial layers to form first inner spacer recesses and second inner spacer recesses, forming first inner spacer features in the first inner spacer recesses, and forming second inner spacer features in the second inner spacer recesses. A composition of the first inner spacer features is different from a composition of the second inner spacer features.
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公开(公告)号:US20220367277A1
公开(公告)日:2022-11-17
申请号:US17815302
申请日:2022-07-27
发明人: Feng-Ching Chu , Wei-Yang Lee , Chia-Pin Lin
IPC分类号: H01L21/8234 , H01L29/66 , H01L21/308 , H01L27/088 , H01L29/08
摘要: A device includes a substrate, an isolation structure over the substrate, and two fins extending from the substrate and above the isolation structure. Two source/drain structures are over the two fins respectively and being side by side along a first direction generally perpendicular to a lengthwise direction of the two fins from a top view . Each of the two source/drain structures has a near-vertical side, the two near-vertical sides facing each other along the first direction. A contact etch stop layer (CESL) is disposed on at least a lower portion of the near-vertical side of each of the two source/drain structures. And two contacts are disposed over the two source/drain structures, respectively, and over the CESL.
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公开(公告)号:US11417767B2
公开(公告)日:2022-08-16
申请号:US17003170
申请日:2020-08-26
发明人: Che-Lun Chang , Wei-Yang Lee , Chia-Pin Lin , Yuan-Ching Peng
IPC分类号: H01L29/786 , H01L23/528 , H01L29/06 , H01L29/423 , H01L29/417 , H01L29/45 , H01L29/78 , H01L21/02 , H01L21/285 , H01L29/66
摘要: Semiconductor devices including backside vias with enlarged backside portions and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; a first dielectric layer on a backside of the first device layer; a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a backside interconnect structure on a backside of the first dielectric layer and the first contact, the first contact including a first portion having first tapered sidewalls and a second portion having second tapered sidewalls, widths of the first tapered sidewalls narrowing in a direction towards the backside interconnect structure, and widths of the second tapered sidewalls widening in a direction towards the backside interconnect structure.
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公开(公告)号:US10224245B2
公开(公告)日:2019-03-05
申请号:US15076762
申请日:2016-03-22
发明人: Chia-Pin Lin , Chien-Tai Chan , Hsien-Chin Lin , Shyue-Shyh Lin
IPC分类号: H01L29/76 , H01L21/8234 , H01L29/06 , H01L29/08 , H01L29/161 , H01L29/78 , H01L21/8238 , H01L29/66 , H01L29/165
摘要: A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between, and a distance between a top surface of the STI region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the STI region. Material is removed from the STI region, to increase the distance between the top surface of the STI region and top surfaces of the first and second fins. A conformal stressor dielectric material is deposited over the fins and STI region. The conformal dielectric stressor material is reflowed, to flow into a space between the first and second fins above a top surface of the STI region, to apply stress to a channel of the finFET.
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公开(公告)号:US20240339542A1
公开(公告)日:2024-10-10
申请号:US18741987
申请日:2024-06-13
发明人: Che-Lun Chang , Wei-Yang Lee , Chia-Pin Lin , Yuan-Ching Peng
IPC分类号: H01L29/786 , H01L21/02 , H01L21/285 , H01L23/528 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/45 , H01L29/66 , H01L29/78
CPC分类号: H01L29/78618 , H01L21/02532 , H01L21/02603 , H01L21/28518 , H01L23/5286 , H01L29/0673 , H01L29/41733 , H01L29/42392 , H01L29/45 , H01L29/66545 , H01L29/66553 , H01L29/66636 , H01L29/66742 , H01L29/7848 , H01L29/78696
摘要: Semiconductor devices including backside vias with enlarged backside portions and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; a first dielectric layer on a backside of the first device layer; a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a backside interconnect structure on a backside of the first dielectric layer and the first contact, the first contact including a first portion having first tapered sidewalls and a second portion having second tapered sidewalls, widths of the first tapered sidewalls narrowing in a direction towards the backside interconnect structure, and widths of the second tapered sidewalls widening in a direction towards the backside interconnect structure.
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