METHODS AND APPARATUS FOR MULTI-PHASE CLOCK GENERATION

    公开(公告)号:US20250007521A1

    公开(公告)日:2025-01-02

    申请号:US18215716

    申请日:2023-06-28

    Abstract: An example apparatus includes: first clock generation circuitry including: interlock circuitry having a terminal; reference clock generation circuitry having a first terminal and a second terminal, the first terminal of the reference clock generation circuitry coupled to the terminal of the interlock circuitry; first duty cycle replication circuitry having a first terminal and a second terminal, the first terminal of the first duty cycle replication circuitry coupled to the second terminal of the reference clock generation circuitry; and buffer circuitry having a first terminal and a second terminal, the first terminal of the buffer circuitry coupled to the second terminal of the first duty cycle replication circuitry; and second clock generation circuitry including: detection circuitry having a first terminal and a second terminal, the first terminal of the detection circuitry coupled to the second terminal of the buffer circuitry; second detection circuitry having a first terminal and a second terminal.

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