Abstract:
Methods, apparatus, systems, and articles of manufacture are disclosed for a multi-level turn-off circuit. An example power delivery circuit includes a two-level turn-off circuit to be coupled to a first switch to reduce a first gate voltage of the first switch from a first voltage to a second voltage when a current flowing through the first switch is greater than an over-current threshold, the two-level turn-off circuit including a second switch, a voltage-current-voltage buffer to reduce a second gate voltage of the second switch from a third voltage to a fourth voltage, and a comparator circuit to turn off the second switch when the second gate voltage is the fourth voltage, and a driver to be coupled to the first switch to turn off the first switch when the second gate voltage is the fourth voltage.
Abstract:
Mode control circuitry is disclosed for use in a buck switching voltage regulator capable of operating in a pulse width modulation (PWM) mode and a pulse frequency modulation (PFM) mode, with the regulator including an inductor having first and second opposite inductor terminals, a first transistor switch connected between the first inductor terminal and a power input terminal and a second transistor switch connected between the first inductor terminal and a circuit common. Current sensing circuitry is provided to sense inductor current through the second switching transistor when the second switching transistor is switched to an ON state and to produce a current sense signal which is integrated over time starting when the second switching transistor is switched to an ON state and to produce a sense signal. The mode switching circuitry switches between the PWM and PFM modes in response to the sense signal.
Abstract:
Methods, apparatus, systems, and articles of manufacture are disclosed for a multi-level turn-off circuit. An example power delivery circuit includes a two-level turn-off circuit to be coupled to a first switch to reduce a first gate voltage of the first switch from a first voltage to a second voltage when a current flowing through the first switch is greater than an over-current threshold, the two-level turn-off circuit including a second switch, a voltage-current-voltage buffer to reduce a second gate voltage of the second switch from a third voltage to a fourth voltage, and a comparator circuit to turn off the second switch when the second gate voltage is the fourth voltage, and a driver to be coupled to the first switch to turn off the first switch when the second gate voltage is the fourth voltage.
Abstract:
Methods, apparatus, systems, and articles of manufacture are disclosed for a multi-level turn-off circuit. An example power delivery circuit includes a two-level turn-off circuit to be coupled to a first switch to reduce a first gate voltage of the first switch from a first voltage to a second voltage when a current flowing through the first switch is greater than an over-current threshold, the two-level turn-off circuit including a second switch, a voltage-current-voltage buffer to reduce a second gate voltage of the second switch from a third voltage to a fourth voltage, and a comparator circuit to turn off the second switch when the second gate voltage is the fourth voltage, and a driver to be coupled to the first switch to turn off the first switch when the second gate voltage is the fourth voltage.
Abstract:
Methods, apparatus, systems, and articles of manufacture are disclosed for a multi-level turn-off circuit. An example power delivery circuit includes a two-level turn-off circuit to be coupled to a first switch to reduce a first gate voltage of the first switch from a first voltage to a second voltage when a current flowing through the first switch is greater than an over-current threshold, the two-level turn-off circuit including a second switch, a voltage-current-voltage buffer to reduce a second gate voltage of the second switch from a third voltage to a fourth voltage, and a comparator circuit to turn off the second switch when the second gate voltage is the fourth voltage, and a driver to be coupled to the first switch to turn off the first switch when the second gate voltage is the fourth voltage.
Abstract:
A buck switching voltage regulator, with high side and low side switching transistors, includes mode control circuitry for switching between PWM and PFM modes based on sensing inductor current through the low side switch during switching cycle OFF times (inductor discharge). Mode switching is based on comparing a an integrated inductor current sense signal with an integrated reference signal corresponding to a predefined average inductor current IAVE. In one embodiment, a mode switching condition is based in part on [IVALLEY=2IAVE−IPEAK], where IPEAK is a detected peak inductor current at the beginning of an OFF time, and IVALLEY is an inductor current value determined by IAVE and IPEAK.