公开(公告)号：US06279081B1

公开(公告)日：2001-08-21

申请号：US09218226

申请日：1998-12-22

申请人： Thomas V Spencer ,  Robert J Horning ,  Monish S Shah

发明人： Thomas V Spencer ,  Robert J Horning ,  Monish S Shah

IPC分类号： G06F1200

CPC分类号： G06F12/0862

摘要： The present invention is generally directed to a system and method for fetching data from a system memory to an ATM card. The method includes the steps of receiving a request (via a PCI bus) to fetch data from memory, and identifying the request as an ATM request. The method then determines, based on the start address, the number of cache lines that will be implicated by the fetch. Then, the method automatically fetches the appropriate number of cache lines into the cache, and then passes the data to the ATM card, via the PCI bus. In accordance with another aspect of the present invention, a system is provided for fetching data from memory for an ATM card. Broadly, the system includes a system memory for data storage and a cache memory for providing high-speed (retrieval) temporary storage of data, the cache memory being disposed in communication with the system memory via a high-speed system bus. The system further includes a PCI bus in communication with the cache memory via an input/output (I/O) bus. A first mechanism is configured to identify a fetch for data from memory to the PCI bus by an ATM card. A second mechanism is configured to determine the number of lines of the cache memory that will be implicated by the identified fetch. Finally, a third mechanism is configured to automatically fetch the appropriate number of lines from the cache memory and to pass the data to the PCI bus.

摘要翻译： 本发明一般涉及一种从系统存储器向ATM卡取出数据的系统和方法。 该方法包括以下步骤：通过PCI总线接收从存储器提取数据的请求，并将该请求识别为ATM请求。 然后，该方法基于开始地址确定将由提取涉及的高速缓存行的数量。 然后，该方法自动将适当数量的高速缓存行提取到高速缓存中，然后通过PCI总线将数据传递到ATM卡。 根据本发明的另一方面，提供一种用于从ATM卡的存储器取出数据的系统。 广泛地说，该系统包括用于数据存储的系统存储器和用于提供数据的高速（检索）临时存储的高速缓冲存储器，该高速缓冲存储器经由高速系统总线被布置为与系统存储器通信。 该系统还包括经由输入/输出（I / O）总线与高速缓冲存储器通信的PCI总线。 第一机制被配置为通过ATM卡识别从存储器到PCI总线的数据的提取。 第二机制被配置为确定将被识别的提取涉及的高速缓冲存储器的行数。 最后，第三种机制被配置为从高速缓冲存储器自动获取适当数量的行并将数据传递到PCI总线。

公开(公告)号：US06542968B1

公开(公告)日：2003-04-01

申请号：US09232293

申请日：1999-01-15

申请人： Thomas V Spencer ,  Robert J Horning

发明人： Thomas V Spencer ,  Robert J Horning

IPC分类号： G06F1200

CPC分类号： G06F12/0875 ,  G06F12/0862 ,  G06F2212/6028

摘要： The present invention is generally directed to a system and method for fetching data from system memory to a device in communication with the system over a PCI bus, via an I/O cache. Broadly, the present invention may be viewed as a novel way to communicate certain fetching hints; namely, hints that specify certain qualities about the data that is to be fetched from the system memory. In operation, the I/O cache may use such hints to more effectively manage the data that passes through it. As simply one example, if, based upon the hints, the controller for the I/O cache knew (or assumed) that the data being fetched was ATM data, then it would also know (based upon the nature of ATM data) that precisely a forty-eight byte data payload was to be sent to the requesting device, and the I/O cache could pre-fetch precisely this amount of data (typically one or two cache lines). In accordance with one aspect of the invention, such a system includes an input/output (I/O) cache memory interposed between the system memory and the PCI bus, wherein the cache memory has internal memory space in the form of a plurality of data lines within the cache memory. The system further includes a plurality of registers for each PCI master that are configured to define fetching criteria. Finally, the system includes a register selector that is configured to select an active register among the plurality of registers, wherein fetching criteria for the device is specified by the active register.

摘要翻译： 本发明一般涉及一种系统和方法，用于经由I / O高速缓存将数据从系统存储器提取到与PCI总线通信的设备。 概括地说，本发明可以被看作是传达某些提取提示的新颖方式; 即指定要从系统内存中提取的数据的某些质量的提示。 在操作中，I / O缓存可以使用这样的提示来更有效地管理通过它的数据。 作为一个例子，如果基于提示，I / O缓存的控制器知道（或假设）所取出的数据是ATM数据，则它也将精确地知道（基于ATM数据的性质）， 将48个字节的数据有效载荷发送到请求设备，并且I / O缓存可以精确地预取这一数量的数据（通常为一个或两个高速缓存行）。 根据本发明的一个方面，这种系统包括插入在系统存储器和PCI总线之间的输入/输出（I / O）高速缓冲存储器，其中高速缓冲存储器具有多个数据形式的内部存储器空间 高速缓存中的行。 该系统还包括用于每个PCI主机的多个寄存器，其被配置为定义提取准则。 最后，该系统包括一个寄存器选择器，被配置为在多个寄存器中选择一个活动寄存器，其中由该寄存器指定该设备的取得标准。

公开(公告)号：US06457105B1

公开(公告)日：2002-09-24

申请号：US09232505

申请日：1999-01-15

申请人： Thomas V Spencer ,  Robert J Horning

发明人： Thomas V Spencer ,  Robert J Horning

IPC分类号： G06F1200

CPC分类号： G06F12/121 ,  G06F2212/303

摘要： The present invention is generally directed to a system and method for providing improved memory management in an asynchronous I/O cache memory. The method includes the steps of identifying a request for data from the system memory by a requesting device that is in communication with the system memory via an I/O bus. Then the method controls the communication of data from the system memory into the cache memory. The method further includes the step of communicating the data from the cache memory to the requesting device, and immediately after communicating the data to the requesting device, the method discards the data from the cache memory. In accordance with the preferred embodiment, the method flushes data from the I/O cache line at a time. Therefore, when a given cache line of data is flushed from the cache after the last data byte of the cache line is communicated out to the requesting device.

摘要翻译： 本发明一般涉及用于在异步I / O高速缓冲存储器中提供改进的存储器管理的系统和方法。 该方法包括以下步骤：通过经由I / O总线与系统存储器通信的请求设备来识别来自系统存储器的数据请求。 然后，该方法控制从系统存储器到高速缓冲存储器的数据通信。 该方法还包括将数据从高速缓冲存储器传送到请求设备，并且在将数据传送到请求设备之后立即将该数据从高速缓冲存储器中丢弃的步骤。 根据优选实施例，该方法一次从I / O高速缓存行刷新数据。 因此，当在高速缓存行的最后一个数据字节被传送到请求设备之后，从缓存中刷新给定的高速缓存行数据时。