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    Matrix transpose hardware acceleration
    4.
    发明授权
    Matrix transpose hardware acceleration 有权

    公开(公告)号：US12125124B1

    公开(公告)日：2024-10-22

    申请号：US18118251

    申请日：2023-03-07

    申请人： Amazon Technologies, Inc.

    发明人： Kun Xu ,  Ron Diamant

    IPC分类号： G06T3/60 ,  G06F12/0862 ,  G06N3/04 ,  G06N3/08 ,  G06T1/60 ,  G06T3/606 ,  G06V10/94

    CPC分类号： G06T1/60 ,  G06F12/0862 ,  G06N3/04 ,  G06N3/08 ,  G06T3/606 ,  G06F2212/455 ,  G06V10/95

    摘要： In one example, an apparatus comprises: a buffer memory; and a memory access circuit configured to: fetch, from a first memory, a set of first groups of data elements of a first matrix, each first group of data elements being stored at consecutive memory addresses at the first memory; based on a first configuration, store the set of first groups of data elements at consecutive memory addresses or at non-consecutive memory addresses at the buffer memory; based on a second configuration that defines a memory address offset, fetch a set of second groups of the data elements from the buffer memory, each second group of the data elements being stored at consecutive memory addresses of the buffer memory, each second group being separated by the memory address offset in the buffer memory; and store each fetched second group at consecutive addresses of a destination memory to form a second matrix.

    Method and apparatus for controlling cache line storage in cache memory
    5.
    发明授权
    Method and apparatus for controlling cache line storage in cache memory 有权

    公开(公告)号：US12124373B2

    公开(公告)日：2024-10-22

    申请号：US18185058

    申请日：2023-03-16

    申请人： ADVANCED MICRO DEVICES, INC.

    发明人： David A. Roberts

    IPC分类号： G06F12/08 ,  G06F12/0815 ,  G06F12/0846 ,  G06F12/0862

    CPC分类号： G06F12/0848 ,  G06F12/0815 ,  G06F12/0862 ,  G06F2212/282 ,  G06F2212/602 ,  G06F2212/621

    摘要： A method and apparatus physically partitions clean and dirty cache lines into separate memory partitions, such as one or more banks, so that during low power operation, a cache memory controller reduces power consumption of the cache memory containing the clean only data. The cache memory controller controls refresh operation so that data refresh does not occur for clean data only banks or the refresh rate is reduced for clean data only banks. Partitions that store dirty data can also store clean data, however other partitions are designated for storing only clean data so that the partitions can have their refresh rate reduced or refresh stopped for periods of time. When multiple DRAM dies or packages are employed, the partition can occur on a die or package level as opposed to a bank level within a die.

    INFORMATION PROCESSING SYSTEM
    6.
    发明公开
    INFORMATION PROCESSING SYSTEM 审中-公开

    公开(公告)号：US20240345774A1

    公开(公告)日：2024-10-17

    申请号：US18630146

    申请日：2024-04-09

    申请人： Kioxia Corporation

    发明人： Shintaro SANO ,  Tomoya SUZUKI ,  Hirotsugu KAJIHARA ,  Kazuhiro HIWADA

    IPC分类号： G06F3/06 ,  G06F12/0862

    CPC分类号： G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0862

    摘要： According to one embodiment, an information processing system includes a processor, a first memory device, and a second memory device including a nonvolatile memory. The nonvolatile memory is accessed by a load/store command. Before issuing a load command to load data stored in the nonvolatile memory, the processor is configured to write a request to instruct prefetching the data to the first memory device. The second memory device includes a controller configured to prefetch the data stored in the nonvolatile memory, based on the request written to the first memory device.

    Prefetch of microservices for incoming requests
    7.
    发明授权
    Prefetch of microservices for incoming requests 有权

    公开(公告)号：US12117936B1

    公开(公告)日：2024-10-15

    申请号：US18190176

    申请日：2023-03-27

    申请人： International Business Machines Corporation

    发明人： Christopher Neil Bailey ,  Matthew Paul Wilson ,  Ian Partridge ,  Sandra Hayward ,  David Richard Jones

    IPC分类号： G06F12/0862

    CPC分类号： G06F12/0862 ,  G06F2212/1024

    摘要： Prefetch of microservices for incoming requests. The method determines for an incoming request a Service Level Objective (SLO) requirement for latency of a request type of the incoming request. The method generates a set of possible microservice sequences for the request including a probability of occurrence of each of the possible microservice sequences and determines a set of prefetch permutations for the set of possible microservice sequences. A latency score is calculated for each prefetch permutation and any prefetch permutations that do not meet the SLO requirement for latency of the request type are eliminated. An optimal prefetch permutation of the remaining prefetch permutations is selected by considering a total cost of the prefetch permutation based on a cost of running each microservice in the set of sequences.

    Processor instructions for data compression and decompression
    9.
    发明授权
    Processor instructions for data compression and decompression 有权

    公开(公告)号：US12106104B2

    公开(公告)日：2024-10-01

    申请号：US17133328

    申请日：2020-12-23

    申请人： Intel Corporation

    发明人： Zhe Wang ,  Alaa R. Alameldeen ,  Christopher J. Hughes

    IPC分类号： G06F9/30 ,  G06F12/0862 ,  H03M7/30

    CPC分类号： G06F9/30047 ,  G06F9/30145 ,  G06F12/0862 ,  H03M7/30 ,  G06F2212/602

    摘要： A processor that includes compression instructions to compress multiple adjacent data blocks of uncompressed read-only data stored in memory into one compressed read-only data block and store the compressed read-only data block in multiple adjacent blocks in the memory is provided. During execution of an application to operate on the read-only data, one of the multiple adjacent blocks storing the compressed read-only block is read from memory, stored in a prefetch buffer and decompressed in the memory controller. In response to a subsequent request during execution of the application for an adjacent data block in the compressed read-only data block, the uncompressed adjacent block is read directly from the prefetch buffer.