WAFER BONDING PROCESS WITH REDUCED OVERLAY DISTORTION

    公开(公告)号:US20240063022A1

    公开(公告)日:2024-02-22

    申请号:US18450083

    申请日:2023-08-15

    CPC classification number: H01L21/187 H01L21/6838 H01L21/3247 H01L22/12

    Abstract: An embodiment method includes determining an upper vacuum condition, a lower vacuum condition, a bonding gap distance, and a striker pressure condition based on measuring residual distortions from a previously bonded wafer. The method includes applying the upper vacuum condition to an upper wafer using an upper wafer holder, the upper vacuum condition applied to a backside of the upper wafer, and the upper wafer having a front side being opposite of the backside. The method includes applying the lower vacuum condition to a lower wafer using a lower wafer holder. The method includes positioning the front side of the upper wafer over the front side of the lower wafer to create the bonding gap distance between the upper wafer and the lower wafer and striking the backside of the upper wafer with a striker using the striker pressure condition to bond the front side of the upper wafer and the front side of the lower wafer together.

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