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    WAFER BONDING APPARATUS AND METHODS TO REDUCE POST-BOND WAFER DISTORTION
    1.
    发明申请
    WAFER BONDING APPARATUS AND METHODS TO REDUCE POST-BOND WAFER DISTORTION 有权

    公开(公告)号：US20220344179A1

    公开(公告)日：2022-10-27

    申请号：US17236785

    申请日：2021-04-21

    Applicant: Tokyo Electron Limited

    Inventor： Nathan Ip

    IPC: H01L21/67

    Abstract: Various embodiments of wafer bonding apparatuses and methods are described herein for reducing distortion in a post-bonded wafer pair. More specifically, the present disclosure provides embodiments of wafer bonding apparatuses and methods to reduce post-bond wafer distortion that occurs primarily within the center and/or the edge of the post-bonded wafer pair. In the present disclosure, post-bonded wafer distortion is reduced by correcting for variations in the pre-bond wafer shapes. Variations in pre-bond wafer shape are corrected, or compensated for, by making hardware modifications to the wafer chuck. Such modifications may include, but are not limited to, modifications to the surface height and/or the temperature of the wafer chuck. Although hardware modifications are disclosed herein for reducing post-bond wafer distortion near the center and/or the edge of the post-bonded wafer pair, similar modifications can be made to reduce post-bond wafer distortion within other areas or zones of the post-bonded wafer pair.

    ENHANCEMENT OF YIELD OF FUNCTIONAL MICROELECTRONIC DEVICES
    2.
    发明申请
    ENHANCEMENT OF YIELD OF FUNCTIONAL MICROELECTRONIC DEVICES 审中-公开

    公开(公告)号：US20190139798A1

    公开(公告)日：2019-05-09

    申请号：US16179492

    申请日：2018-11-02

    Applicant: Tokyo Electron Limited

    Inventor： Carlos A. Fonseca ,  Nathan Ip ,  Joel Estrella

    IPC: H01L21/67 ,  H01L21/66

    Abstract: Described herein are techniques related to a semiconductor fabrication process that facilitates the enhancement of systemic conformities of patterns of the fabricated semiconductor wafer. A semiconductor wafer with maximized systemic conformities of patterns will maximize the electrical properties and/or functionality of the electronic devices formed as part of the fabricated semiconductor wafer. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

    WAFER BONDING PROCESS WITH REDUCED OVERLAY DISTORTION
    3.
    发明公开
    WAFER BONDING PROCESS WITH REDUCED OVERLAY DISTORTION 审中-公开

    公开(公告)号：US20240063022A1

    公开(公告)日：2024-02-22

    申请号：US18450083

    申请日：2023-08-15

    Applicant: Tokyo Electron Limited

    Inventor： Christopher Michael Netzband ,  Nathan Ip

    IPC: H01L21/18 ,  H01L21/683 ,  H01L21/324 ,  H01L21/66

    CPC classification number: H01L21/187 ,  H01L21/6838 ,  H01L21/3247 ,  H01L22/12

    Abstract: An embodiment method includes determining an upper vacuum condition, a lower vacuum condition, a bonding gap distance, and a striker pressure condition based on measuring residual distortions from a previously bonded wafer. The method includes applying the upper vacuum condition to an upper wafer using an upper wafer holder, the upper vacuum condition applied to a backside of the upper wafer, and the upper wafer having a front side being opposite of the backside. The method includes applying the lower vacuum condition to a lower wafer using a lower wafer holder. The method includes positioning the front side of the upper wafer over the front side of the lower wafer to create the bonding gap distance between the upper wafer and the lower wafer and striking the backside of the upper wafer with a striker using the striker pressure condition to bond the front side of the upper wafer and the front side of the lower wafer together.

    Method and process using fingerprint based semiconductor manufacturing process fault detection
    7.
    发明授权
    Method and process using fingerprint based semiconductor manufacturing process fault detection 有权

    公开(公告)号：US11868119B2

    公开(公告)日：2024-01-09

    申请号：US17484204

    申请日：2021-09-24

    Applicant: Tokyo Electron Limited

    Inventor： Nathan Ip ,  Megan Wooley

    IPC: G05B19/418 ,  G06F30/31

    CPC classification number: G05B19/4184 ,  G05B19/41805 ,  G05B19/41885 ,  G06F30/31

    Abstract: Sensitivity calculations are provided of a process model through the rate of change of a model fingerprint with respect to process variables and defects. A fingerprint sensitivity table is generated, where process variables are associated with a set of fingerprint sensitivities. The fingerprint of incoming substrates is monitored through a production process by applying the same fingerprint method that is used in the process model. Calculations are made of the difference between the incoming substrate fingerprint and the process model predicted fingerprint. This difference fingerprint is compared against the table of fingerprint sensitivities to find the process variable most likely to be responsible for the difference. Spatial relationships between process variables and actual measurements on the substrate may be obtained. Correlation through fingerprint sensitivity improves the ability to pinpoint faulty process tools. The difference fingerprint may also identify the formation of defects on a substrate.

    Plasma processing method and plasma processing apparatus
    8.
    发明授权
    Plasma processing method and plasma processing apparatus 有权

    公开(公告)号：US11574808B2

    公开(公告)日：2023-02-07

    申请号：US17176446

    申请日：2021-02-16

    Applicant: Tokyo Electron Limited

    Inventor： Satoshi Itoh ,  Norifumi Kohama ,  Soudai Emori ,  Nathan Ip

    IPC: H01L21/02 ,  C23C16/34 ,  H01L21/66 ,  H01J37/32 ,  C23C16/50 ,  C23C16/52

    Abstract: A plasma processing method that is executed by a plasma processing apparatus including a processing container containing a target substrate, a plurality of plasma sources, and a gas supply apparatus for supplying gas includes: supplying the gas from the gas supply apparatus into the processing container; individually controlling intensity of power introduced from each of the plurality of plasma sources into the processing container; and generating plasma of the gas by the intensity of the power introduced from each of the plurality of plasma sources and depositing a desired film on a second surface of the target substrate that is an opposite surface of a first surface of the target substrate so as to apply desired film stress to a film on the first surface.

    Apparatus and Methods for Wafer to Wafer Bonding
    9.
    发明申请
    Apparatus and Methods for Wafer to Wafer Bonding 有权

    公开(公告)号：US20220013416A1

    公开(公告)日：2022-01-13

    申请号：US16924847

    申请日：2020-07-09

    Applicant: Tokyo Electron Limited

    Inventor： Nathan Ip

    IPC: H01L21/66 ,  H01L23/00 ,  G06F30/27 ,  H01L21/18

    Abstract: A method includes having a first wafer bonding recipe and a model of a wafer bonding process, the model comprising an input indicative of a physical parameter of a first wafer to be bonded to a second wafer and configured to output a wafer bonding recipe based on the physical parameter of the first wafer; obtaining measurements of the first wafer to obtain the physical parameter of the first wafer; generating, by the model, the first wafer bonding recipe based on the physical parameter of the first wafer; and bonding the first wafer to the second wafer in accordance with the first wafer bonding recipe to produce a first post-bond wafer.

    ENHANCEMENT OF YIELD OF FUNCTIONAL MICROELECTRONIC DEVICES
    10.
    发明申请
    ENHANCEMENT OF YIELD OF FUNCTIONAL MICROELECTRONIC DEVICES 审中-公开

    公开(公告)号：US20190137565A1

    公开(公告)日：2019-05-09

    申请号：US16179526

    申请日：2018-11-02

    Applicant: Tokyo Electron Limited

    Inventor： Carlos A. Fonseca ,  Nathan Ip ,  Joel Estrella

    IPC: G01R31/28 ,  G06F17/50 ,  G01R1/02

    Abstract: Described herein are techniques related to a semiconductor fabrication process that facilitates the enhancement of systemic conformities of patterns of the fabricated semiconductor wafer. A semiconductor wafer with maximized systemic conformities of patterns will maximize the electrical properties and/or functionality of the electronic devices formed as part of the fabricated semiconductor wafer. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

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