公开(公告)号：US11784214B2

公开(公告)日：2023-10-10

申请号：US17899807

申请日：2022-08-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Bo-Wei Huang ,  Chun-Wei Kang ,  Ho-Yu Lai ,  Chih-Sheng Chang

IPC: H01L23/64 ,  H01L49/02

CPC classification number: H01L28/84 ,  H01L23/642 ,  H01L28/40

Abstract: A method for fabricating a metal-insulator-metal (MIM) capacitor is provided. The MIM capacitor includes a substrate, a first metal layer, a deposition structure, a dielectric layer and a second metal layer. The first metal layer is disposed on the substate and has a planarized surface. The deposition structure is disposed on the first metal layer, and at least a portion of the deposition structure extends into the planarized surface, wherein the first metal layer and the deposition structure have the same material. The dielectric layer is disposed on the deposition structure. The second metal layer is disposed on the dielectric layer.

公开(公告)号：US11469294B2

公开(公告)日：2022-10-11

申请号：US16862827

申请日：2020-04-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Bo-Wei Huang ,  Chun-Wei Kang ,  Ho-Yu Lai ,  Chih-Sheng Chang

IPC: H01L49/02 ,  H01L23/64

Abstract: A metal-insulator-metal (MIM) capacitor includes a substrate, a first metal layer, a deposition structure, a dielectric layer and a second metal layer. The first metal layer is disposed on the substrate and has a planarized surface. The deposition structure is disposed on the first metal layer, and at least a portion of the deposition structure extends into the planarized surface, wherein the first metal layer and the deposition structure have the same material. The dielectric layer is disposed on the deposition structure. The second metal layer is disposed on the dielectric layer.

公开(公告)号：US20240266286A1

公开(公告)日：2024-08-08

申请号：US18118093

申请日：2023-03-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Bo-Wei Huang ,  Po-Hung Chen ,  Chun-Cheng Yu ,  I-Hsien Liu ,  Ho-Yu Lai ,  Kuan-Wen Fang ,  Chih-Sheng Chang

IPC: H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76892

Abstract: A semiconductor pattern is provided in the present invention, including a first line extending to one end in a first direction and a second line extending in a second direction perpendicular to the first direction and adjacent to the end of the first line in the first direction, wherein the end of the first line is provided with a rounding feature, the first line has a width in the second direction, and the width is gradually increased to a maximum width toward the end and gradually converged to form the rounding feature.