公开(公告)号：US11854817B2

公开(公告)日：2023-12-26

申请号：US17669970

申请日：2022-02-11

Applicant: KEY FOUNDRY CO., LTD.

Inventor： Seung Mo Jo

IPC: H01L21/3065 ,  H01L49/02

CPC classification number: H01L21/30655 ,  H01L28/84 ,  H01L28/87 ,  H01L28/91

Abstract: A manufacturing method for a deep trench, the method includes forming a first trench in a substrate and performing a first cycle and a second cycle. Each comprising performing a passivation operation forming a passivation film on a sidewall and a bottom surface of the first trench, performing a first etching with a first bias power to remove the passivation film formed on the bottom surface of the first trench to expose the bottom surface of the first trench, and performing a second etching with a second bias power etching the exposed bottom surface of the first trench to form a second trench disposed below the first trench. The first bias power and the second bias power in the second cycle is greater than the first bias power and the second bias power in the first cycle, respectively.

公开(公告)号：US20180226470A1

公开(公告)日：2018-08-09

申请号：US15873913

申请日：2018-01-18

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Tien-Chen Chan ,  Shu-Yen Chan ,  Chi-Mao Hsu ,  Shih-Fang Tzou

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/84 ,  H01L27/10808 ,  H01L27/10852 ,  H01L28/90 ,  H01L28/91

Abstract: A method of fabricating a bottom electrode includes providing a dielectric layer. An atomic layer deposition is performed to form a bottom electrode material on the dielectric layer. Then, an oxidation process is performed to oxidize part of the bottom electrode material. The oxidized bottom electrode material transforms into an oxide layer. The bottom electrode material which is not oxidized becomes a bottom electrode. A top surface of the bottom electrode includes numerous hill-like profiles. Finally, the oxide layer is removed.

公开(公告)号：US20180114640A1

公开(公告)日：2018-04-26

申请号：US15849815

申请日：2017-12-21

Applicant: Murata Manufacturing Co., Ltd.

Inventor： NORIYUKI INOUE ,  Kazuo Hattori ,  Hiromasa Saeki

IPC: H01G4/08 ,  H01G4/248 ,  H01G4/33

CPC classification number: H01G4/08 ,  H01G4/248 ,  H01G4/33 ,  H01G9/012 ,  H01G9/0425 ,  H01G9/048 ,  H01G9/052 ,  H01G9/07 ,  H01G9/15 ,  H01L28/84

Abstract: A capacitor having an element main body including a metal high specific surface area substrate which has fine pores formed therein and has a large specific surface area; a dielectric layer in a prescribed region on the surface of the high specific surface area substrate including the inner surfaces of the pores; and a conductive part on the dielectric layer. A first terminal electrode is electrically connected to the high specific surface area substrate. A second terminal electrode is electrically connected to the conductive part. The element main body includes a first region that contributes to the acquisition of the capacitance and second regions having a smaller void ratio than the first region. The second regions have a void ratio of 25% or less.

公开(公告)号：US20170317161A1

公开(公告)日：2017-11-02

申请号：US15142332

申请日：2016-04-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Ming-Cheng Chang ,  Ralf Richter

IPC: H01L49/02

CPC classification number: H01L28/84 ,  H01L21/76283 ,  H01L28/40 ,  H01L28/82

Abstract: The present disclosure provides a method of forming a capacitor structure and a capacitor structure. A semiconductor-on-insulator substrate is provided comprising a semiconductor layer, a buried insulating material layer and a semiconductor substrate material. A shallow trench isolation structure defining a first active region on the SOI substrate is formed, the first active region having a plurality of trenches formed therein. Within each trench, the semiconductor substrate material is exposed on inner sidewalls and a bottom face. A layer of insulating material covering the exposed semiconductor substrate material is formed, and an electrode material is deposited on the layer of insulating material in the first active region.

公开(公告)号：US20170025324A1

公开(公告)日：2017-01-26

申请号：US15217111

申请日：2016-07-22

Applicant: TDK CORPORATION

Inventor： Masahiro YAMAKI ,  Hitoshi SAITA

IPC: H01L23/367 ,  H01G4/12 ,  H01L23/498 ,  H01G2/14 ,  H01L23/00 ,  H01L23/42 ,  H01G4/33 ,  H01G4/005

CPC classification number: H01L23/42 ,  H01G2/14 ,  H01G4/005 ,  H01G4/012 ,  H01G4/1227 ,  H01G4/224 ,  H01G4/33 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L28/82 ,  H01L28/84 ,  H01L2224/16265 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19102

Abstract: The present invention provides a thin film capacitor including a first electrode layer, a second electrode layer, and a dielectric layer provided between the first electrode layer and the second electrode layer, wherein a ratio (S/S0) of a surface area S of a surface of the first electrode layer on an opposite side to the dielectric layer to a projected area S0 in a thickness direction of the first electrode layer is 1.01 to 5.00.

Abstract translation: 本发明提供了一种薄膜电容器，其包括设置在第一电极层和第二电极层之间的第一电极层，第二电极层和电介质层，其中，表面积S的比率（S / S0） 第一电极层的与电介质层相反的一侧的表面与第一电极层的厚度方向上的投影面积S0为1.01〜5.00。

公开(公告)号：US09178117B2

公开(公告)日：2015-11-03

申请号：US14057341

申请日：2013-10-18

Applicant: LG INNOTEK CO., LTD.

Inventor： Han Byul Kang

IPC: H01L27/15 ,  H01L29/165 ,  H01L31/12 ,  H01L33/00 ,  H01L27/14 ,  H01L31/0232 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L33/44 ,  H01L21/285 ,  H01L33/40 ,  H01L21/02 ,  H01L21/768 ,  H01L23/532 ,  H01L49/02 ,  H01L33/32

CPC classification number: H01L33/44 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/28575 ,  H01L21/76841 ,  H01L23/53223 ,  H01L23/53266 ,  H01L28/84 ,  H01L33/32 ,  H01L33/40 ,  H01L2224/4051 ,  H01L2224/45139 ,  H01L2224/4851 ,  H01L2924/00014 ,  H01L2924/00011 ,  H01L2224/37099

Abstract: A light emitting device includes a light emitting structure including a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, and a second conductive semiconductor layer on the active layer, and an electrode on at least one of the first conductive semiconductor layers or the second semiconductor layer. The electrode includes an adhesive layer on the light emitting structure, a barrier layer on the adhesive layer, and a bonding layer on the barrier layer. The barrier layer includes a plurality of grain boundaries, and the grain boundaries include interstitial elements.

Abstract translation: 发光器件包括发光结构，其包括第一导电半导体层，第一导电半导体层上的有源层和有源层上的第二导电半导体层，以及至少一个第一导电半导体层上的电极 或第二半导体层。 该电极包括在发光结构上的粘合剂层，粘合剂层上的阻挡层和阻挡层上的结合层。 阻挡层包括多个晶界，并且晶界包括间隙元素。

公开(公告)号：US20150194478A1

公开(公告)日：2015-07-09

申请号：US14147424

申请日：2014-01-03

Applicant: Micron Technology, Inc.

Inventor： Vassil N. Antonov ,  Vishwanath Bhat

IPC: H01L49/02

CPC classification number: H01L28/84 ,  H01L28/91

Abstract: A method of forming a capacitor includes forming an elevationally elongated and elevationally inner capacitor electrode that comprises different composition laterally-outermost and laterally-innermost conductive portions that have different respective intrinsic residual mechanical stress. The innermost conductive portion is formed to have greater mechanical stress in the compressive direction than the outermost conductive portion. A capacitor dielectric is formed over the inner capacitor electrode and an elevationally outer capacitor electrode is formed over the capacitor dielectric. A capacitor construction independent of the method formed is disclosed.

Abstract translation: 形成电容器的方法包括形成具有不同组成的横向最外侧和最外层的导电部分的具有不同的各自的本征残余机械应力的不规则的细长的和垂直内部的电容器电极。 最内侧的导电部形成为具有比最外侧导电部更大的压缩方向的机械应力。 在内部电容器电极上形成电容器电介质，并且在电容器电介质上方形成正面外部的电容器电极。 公开了独立于所形成方法的电容器结构。

公开(公告)号：US08975682B2

公开(公告)日：2015-03-10

申请号：US12861256

申请日：2010-08-23

Applicant: Aomar Halimaoui ,  Rebha El Farhane ,  Benoit Froment

Inventor： Aomar Halimaoui ,  Rebha El Farhane ,  Benoit Froment

IPC: H01L29/94 ,  H01L27/108 ,  H01L49/02

CPC classification number: H01L28/84 ,  H01L28/90

Abstract: An integrated circuit (IC) includes at least one capacitor with metal electrodes. At least one of the electrodes (10 or 30) is formed from at least surface-silicided hemispherical grain silicon or silicon alloy. A fabrication process for obtaining such a capacitor with silicided metal electrodes is also provided.

Abstract translation: 集成电路（IC）包括至少一个具有金属电极的电容器。 至少一个电极（10或30）由至少表面硅化半球形硅或硅合金形成。 还提供了用硅化金属电极获得这种电容器的制造工艺。

公开(公告)号：US08816447B2

公开(公告)日：2014-08-26

申请号：US13751467

申请日：2013-01-28

Applicant: Round Rock Resarch, LLC

Inventor： Shuang Meng ,  Garo J. Derderian ,  Gurtej S. Sandhu

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/511 ,  C23C16/45542 ,  C23C16/515 ,  H01L21/02183 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/3141 ,  H01L21/76843 ,  H01L28/75 ,  H01L28/84 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: Devices such as transistors having an oxide layer that provide a depletion field in a conduction channel. A barrier layer is formed over the oxide layer. A gate electrode is formed over the barrier layer. The barrier layer and gate electrode are configured to reduce the width of the depletion field absent a voltage applied to the gate electrode.

Abstract translation: 诸如具有在传导通道中提供耗尽场的氧化物层的晶体管的器件。 在氧化物层上形成阻挡层。 在阻挡层上形成栅电极。 阻挡层和栅电极被配置为在没有施加到栅电极的电压的情况下减小耗尽场的宽度。

公开(公告)号：US08362576B2

公开(公告)日：2013-01-29

申请号：US13006789

申请日：2011-01-14

Applicant: Shuang Meng ,  Garo J. Derderian ,  Gurtej S. Sandhu

Inventor： Shuang Meng ,  Garo J. Derderian ,  Gurtej S. Sandhu

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L23/58 ,  H01L27/148 ,  H01L29/768 ,  H01L29/74 ,  H01L29/96 ,  H01L31/111 ,  H01L29/34

CPC classification number: H01L29/511 ,  C23C16/45542 ,  C23C16/515 ,  H01L21/02183 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/3141 ,  H01L21/76843 ,  H01L28/75 ,  H01L28/84 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: Atomic layer deposition is enhanced using plasma. Plasma begins prior to flowing a second precursor into a chamber. The second precursor reacts with a first precursor to deposit a layer on a substrate. The layer may include at least one element from each of the first and second precursors. The layer may be TaN, and the precursors may be TaF5 and NH3. The plasma may begin during purge gas flow between a pulse of the first precursor and a pulse of the second precursor. Thermal energy assists the reaction of the precursors to deposit the layer on the substrate. The thermal energy may be greater than generally accepted for ALD (e.g., more than 300 degrees Celsius).

Abstract translation: 使用等离子体增强原子层沉积。 等离子体在将第二前体流入室之前开始。 第二前体与第一前体反应以在衬底上沉积一层。 该层可以包括来自第一和第二前体中的每一个的至少一种元素。 该层可以是TaN，前体可以是TaF5和NH3。 等离子体可以在第一前体的脉冲和第二前体的脉冲之间的净化气流期间开始。 热能有助于前体的反应，以将该层沉积在基底上。 热能可能大于ALD普遍接受的热能（例如，超过300摄氏度）。