公开(公告)号：US10366978B1

公开(公告)日：2019-07-30

申请号：US16036914

申请日：2018-07-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Hsiang Chang ,  Hou-Jen Chiu ,  Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08

Abstract: A grounded gate NMOS transistor includes a P-type substrate, P-well region in the P-type substrate, and a gate finger traversing the P-well region. The gate finger has a first spacer on a first sidewall and a second spacer on a second sidewall opposite to the first sidewall. An N+ drain doping region is disposed in the P-type substrate and is adjacent to the first sidewall of the gate finger. The N+ drain doping region is contiguous with a bottom edge of the first spacer. An N+ source doping region is disposed in the P-type substrate opposite to the N+ drain doping region. The N+ source doping region is kept a predetermined distance from a bottom edge of the second spacer. A P+ pick-up ring is disposed in the P-well region and surrounds the gate finger, the N+ drain doping region, and the N+ source doping region.