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公开(公告)号:US11381247B1
公开(公告)日:2022-07-05
申请号:US17225074
申请日:2021-04-07
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Wen-Hong Hsu , Po-Hua Chen , Yu-Yee Liow , Chih-Wei Wu , Hsuan-Chih Yeh
Abstract: An apparatus includes a phase-locked loop and a jitter detection circuit. A method of detecting a jitter in the apparatus includes the phase-locked loop generating a lead control signal and a lag control signal according to a reference clock and a feedback clock, the jitter detection circuit generating a jitter signal according to the lead control signal and the lag control signal, the jitter detection circuit generating a jitter window signal according to the jitter signal, the jitter detection circuit identifying jitters in the clock signal according to the jitter signal and the jitter window signal, and the jitter detection circuit outputting a jitter indication signal according to the number of jitters identified.
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公开(公告)号:US12250002B2
公开(公告)日:2025-03-11
申请号:US18127262
申请日:2023-03-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Po-Hua Chen , Yu-Yee Liow , Chih-Wei Wu , Wen-Hong Hsu , Hsuan-Chih Yeh , Pei-Wen Sun
IPC: H03M1/46
Abstract: A SAR ADC includes: a sample-hold (S/H) circuit sampling an input voltage to generate a S/H output signal; a DAC generating a DAC output signal; a comparator comparing the DAC output signal with the S/H output signal to generate a comparison output signal; a SAR combinational digital circuit group; a multiplexer circuit; and a plurality of registers for registering the comparison output signal as register output signals and outputting as an output signal of the SAR ADC. The SAR combinational digital circuit group generates a plurality of first and second SAR output signals based on the register output signals. The multiplexer circuit is controlled by on the register output signals to select among the first and the second SAR output signals as a plurality of multiplexer output signals for sending to the DAC. A capacitor coupling relationship of the DAC is controlled by the multiplexer output signals.
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