公开(公告)号：US20240063052A1

公开(公告)日：2024-02-22

申请号：US17949186

申请日：2022-09-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tzu-Feng Weng ,  Chao-Sheng Cheng ,  Chi-Cheng Huang

IPC: H01L21/762 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/76264 ,  H01L21/28141 ,  H01L29/66545

Abstract: A manufacturing method of a gate structure includes the following steps. A semiconductor substrate is provided. An isolation structure is formed in the semiconductor substrate and surrounds an active region in the semiconductor substrate. A gate pattern is formed on the active region and the isolation structure. The gate pattern includes a first gate structure and a first capping layer disposed on the first gate structure. A part of the first capping layer located above an interface between the active region and the isolation structure is removed for exposing a part of the first gate structure located above the interface between the active region and the isolation structure. A removing process is performed for reducing a thickness of the part of the first gate structure located above the interface between the active region and the isolation structure.