公开(公告)号：US12191182B2

公开(公告)日：2025-01-07

申请号：US17987867

申请日：2022-11-16

Applicant: United Microelectronics Corp.

Inventor： Nuo Wei Luo ,  Huabiao Wu

IPC: H01L21/68 ,  G03F7/00 ,  H01L21/027 ,  H01L23/544

Abstract: Provided is a semiconductor device includes a substrate, an isolation structure, an alignment mark, and a dielectric layer. The substrate includes a first region and a second region. The isolation structure is disposed in the substrate in the first region, wherein the isolation structure extends from a first surface of the substrate toward a second surface of the substrate.
The alignment mark is disposed in the substrate in the second region. The alignment mark extends from the first surface of the substrate toward the second surface of the substrate and at the same level as the isolation structure. The dielectric layer is buried in the substrate in the second region and overlapping the alignment mark.

公开(公告)号：US20210384059A1

公开(公告)日：2021-12-09

申请号：US16931277

申请日：2020-07-16

Applicant: United Microelectronics Corp.

Inventor： Nuo Wei Luo ,  Huabiao Wu

IPC: H01L21/68 ,  H01L23/544 ,  G03F7/20 ,  H01L21/027

Abstract: Provided is a method of manufacturing a semiconductor device, including providing a substrate including a first region and a second region; forming an alignment mark in the substrate in the second region; forming a material layer on a first surface of the substrate in the first region and the second region; introducing heteroatoms into the substrate in the second region from a second surface of the substrate; and reacting the heteroatoms with the substrate to form a dielectric layer overlapping the alignment mark in the substrate in the second region.

公开(公告)号：US20230073022A1

公开(公告)日：2023-03-09

申请号：US17987867

申请日：2022-11-16

Applicant: United Microelectronics Corp.

Inventor： Nuo Wei Luo ,  Huabiao Wu

IPC: H01L21/68 ,  H01L21/027 ,  G03F7/20 ,  H01L23/544

Abstract: Provided is a semiconductor device includes a substrate, an isolation structure, an alignment mark, and a dielectric layer. The substrate includes a first region and a second region. The isolation structure is disposed in the substrate in the first region, wherein the isolation structure extends from a first surface of the substrate toward a second surface of the substrate.
The alignment mark is disposed in the substrate in the second region. The alignment mark extends from the first surface of the substrate toward the second surface of the substrate and at the same level as the isolation structure. The dielectric layer is buried in the substrate in the second region and overlapping the alignment mark.

公开(公告)号：US11527428B2

公开(公告)日：2022-12-13

申请号：US16931277

申请日：2020-07-16

Applicant: United Microelectronics Corp.

Inventor： Nuo Wei Luo ,  Huabiao Wu

IPC: H01L21/68 ,  H01L21/027 ,  G03F7/20 ,  H01L23/544

Abstract: Provided is a method of manufacturing a semiconductor device, including providing a substrate including a first region and a second region; forming an alignment mark in the substrate in the second region; forming a material layer on a first surface of the substrate in the first region and the second region; introducing heteroatoms into the substrate in the second region from a second surface of the substrate; and reacting the heteroatoms with the substrate to form a dielectric layer overlapping the alignment mark in the substrate in the second region.