公开(公告)号：US20230073022A1

公开(公告)日：2023-03-09

申请号：US17987867

申请日：2022-11-16

Applicant: United Microelectronics Corp.

Inventor： Nuo Wei Luo ,  Huabiao Wu

IPC: H01L21/68 ,  H01L21/027 ,  G03F7/20 ,  H01L23/544

Abstract: Provided is a semiconductor device includes a substrate, an isolation structure, an alignment mark, and a dielectric layer. The substrate includes a first region and a second region. The isolation structure is disposed in the substrate in the first region, wherein the isolation structure extends from a first surface of the substrate toward a second surface of the substrate.
The alignment mark is disposed in the substrate in the second region. The alignment mark extends from the first surface of the substrate toward the second surface of the substrate and at the same level as the isolation structure. The dielectric layer is buried in the substrate in the second region and overlapping the alignment mark.

公开(公告)号：US11527428B2

公开(公告)日：2022-12-13

申请号：US16931277

申请日：2020-07-16

Applicant: United Microelectronics Corp.

Inventor： Nuo Wei Luo ,  Huabiao Wu

IPC: H01L21/68 ,  H01L21/027 ,  G03F7/20 ,  H01L23/544

Abstract: Provided is a method of manufacturing a semiconductor device, including providing a substrate including a first region and a second region; forming an alignment mark in the substrate in the second region; forming a material layer on a first surface of the substrate in the first region and the second region; introducing heteroatoms into the substrate in the second region from a second surface of the substrate; and reacting the heteroatoms with the substrate to form a dielectric layer overlapping the alignment mark in the substrate in the second region.

公开(公告)号：US12191182B2

公开(公告)日：2025-01-07

申请号：US17987867

申请日：2022-11-16

Applicant: United Microelectronics Corp.

Inventor： Nuo Wei Luo ,  Huabiao Wu

IPC: H01L21/68 ,  G03F7/00 ,  H01L21/027 ,  H01L23/544

Abstract: Provided is a semiconductor device includes a substrate, an isolation structure, an alignment mark, and a dielectric layer. The substrate includes a first region and a second region. The isolation structure is disposed in the substrate in the first region, wherein the isolation structure extends from a first surface of the substrate toward a second surface of the substrate.
The alignment mark is disposed in the substrate in the second region. The alignment mark extends from the first surface of the substrate toward the second surface of the substrate and at the same level as the isolation structure. The dielectric layer is buried in the substrate in the second region and overlapping the alignment mark.

公开(公告)号：US20210384059A1

公开(公告)日：2021-12-09

申请号：US16931277

申请日：2020-07-16

Applicant: United Microelectronics Corp.

Inventor： Nuo Wei Luo ,  Huabiao Wu

IPC: H01L21/68 ,  H01L23/544 ,  G03F7/20 ,  H01L21/027

Abstract: Provided is a method of manufacturing a semiconductor device, including providing a substrate including a first region and a second region; forming an alignment mark in the substrate in the second region; forming a material layer on a first surface of the substrate in the first region and the second region; introducing heteroatoms into the substrate in the second region from a second surface of the substrate; and reacting the heteroatoms with the substrate to form a dielectric layer overlapping the alignment mark in the substrate in the second region.

公开(公告)号：US09305130B2

公开(公告)日：2016-04-05

申请号：US14445037

申请日：2014-07-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jie Zhao ,  Huabiao Wu

IPC: H01L29/66 ,  G06F17/50 ,  H01L29/78 ,  H01L29/417

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  H01L29/41758 ,  H01L29/78 ,  Y10T428/24612

Abstract: A method for forming semiconductor layout patterns providing a pair of first layout patterns being symmetrical along an axial line, each of the first layout patterns comprising a first side proximal to the axial line and a second side far from the axial line; shifting a portion of the first layout patterns toward a direction opposite to the axial line to form at least a first shifted portion in each first layout pattern, and outputting the first layout patterns and the first shifted portions on a first mask.

Abstract translation: 一种用于形成半导体布局图案的方法，其提供沿着轴线对称的一对第一布局图案，所述第一布局图案中的每一个包括靠近所述轴线的第一侧和远离所述轴线的第二侧; 将所述第一布局图案的一部分朝着与所述轴线相反的方向移动，以在每个第一布局图案中形成至少第一偏移部分，并将所述第一布局图案和所述第一偏移部分输出在第一掩模上。

公开(公告)号：US20140337809A1

公开(公告)日：2014-11-13

申请号：US14445037

申请日：2014-07-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jie Zhao ,  Huabiao Wu

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  H01L29/41758 ,  H01L29/78 ,  Y10T428/24612

Abstract: A method for forming semiconductor layout patterns providing a pair of first layout patterns being symmetrical along an axial line, each of the first layout patterns comprising a first side proximal to the axial line and a second side far from the axial line; shifting a portion of the first layout patterns toward a direction opposite to the axial line to form at least a first shifted portion in each first layout pattern, and outputting the first layout patterns and the first shifted portions on a first mask.

Abstract translation: 一种用于形成半导体布局图案的方法，其提供沿着轴线对称的一对第一布局图案，所述第一布局图案中的每一个包括靠近所述轴线的第一侧和远离所述轴线的第二侧; 将所述第一布局图案的一部分朝着与所述轴线相反的方向移动，以在每个第一布局图案中形成至少第一偏移部分，并将所述第一布局图案和所述第一偏移部分输出在第一掩模上。