公开(公告)号：US12255111B2

公开(公告)日：2025-03-18

申请号：US17394197

申请日：2021-08-04

Applicant: United Microelectronics Corp.

Inventor： Jia Fang Wu ,  Hsiang-Chieh Yen ,  Hsu-Sheng Huang ,  Zhi Jian Wang

IPC: H01L21/66 ,  H01L23/522

Abstract: Provided are a multiple-level interconnect structure having a scatterometry test layer and a manufacturing method thereof. The multiple level interconnect structure includes a patterned reflective layer, a bulk reflective layer and a patterned test layer. The patterned reflective layer is disposed on a substrate and includes a first reflective pattern and a second reflective pattern separated from each other. The bulk reflective layer is disposed on the patterned reflective layer. The patterned test layer is disposed on the bulk reflective layer.

公开(公告)号：US20220415724A1

公开(公告)日：2022-12-29

申请号：US17394197

申请日：2021-08-04

Applicant: United Microelectronics Corp.

Inventor： Jia Fang Wu ,  Hsiang-Chieh Yen ,  Hsu-Sheng Huang ,  Zhi Jian Wang

IPC: H01L21/66 ,  H01L23/522

Abstract: Provided are a multiple-level interconnect structure having a scatterometry test layer and a manufacturing method thereof. The multiple level interconnect structure includes a patterned reflective layer, a bulk reflective layer and a patterned test layer. The patterned reflective layer is disposed on a substrate and includes a first reflective pattern and a second reflective pattern separated from each other. The bulk reflective layer is disposed on the patterned reflective layer. The patterned test layer is disposed on the bulk reflective layer.