公开(公告)号：US10430186B2

公开(公告)日：2019-10-01

申请号：US15796635

申请日：2017-10-27

Applicant: VMware, Inc.

Inventor： Irina Calciu ,  Jayneel Gandhi ,  Pradeep Fernando ,  Aasheesh Kolli

IPC: G06F3/06 ,  G06F9/30 ,  G06F11/14 ,  G06F12/0804 ,  G06F12/0868 ,  G06F9/46

Abstract: The disclosure provides an approach for atomically executing computer instructions by a CPU of a computing device comprising non-volatile memory, the CPU configured to implement hardware transactional memory (HTM). The approach generally includes reading an instruction within a section of code designated as an HTM transaction, determining whether the instruction causes a data conflict with another thread, and copying cache lines from memory into a cache of the CPU. The approach further includes marking the copied cache lines as transactional, processing the instruction to create a persistent log within non-volatile memory, and unmarking the copied cache lines from transactional, to non-transactional.