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    Smart prefetching for remote memory
    1.
    发明授权
    Smart prefetching for remote memory 有权

    公开(公告)号：US11586545B2

    公开(公告)日：2023-02-21

    申请号：US17367048

    申请日：2021-07-02

    Applicant: VMware, Inc.

    Inventor： Irina Calciu ,  Andreas Nowatzyk ,  Isam Wadih Akkawi ,  Venkata Subhash Reddy Peddamallu ,  Pratap Subrahmanyam

    IPC: G06F12/0862

    Abstract: Memory pages of a local application program are prefetched from a memory of a remote host. A method of prefetching the memory pages from the remote memory includes detecting that a cache-line access made by a processor executing the local application program is an access to a cache line containing page table data of the local application program, identifying data pages that are referenced by the page table data, and fetching the identified data pages from the remote memory and storing the fetched data pages in a local memory.

    Failure-atomic persistent memory logging using binary translation
    3.
    发明授权
    Failure-atomic persistent memory logging using binary translation 有权

    公开(公告)号：US10817389B2

    公开(公告)日：2020-10-27

    申请号：US16256567

    申请日：2019-01-24

    Applicant: VMware, Inc.

    Inventor： Aasheesh Kolli ,  Irina Calciu ,  Jayneel Gandhi ,  Pratap Subrahmanyam

    IPC: G06F11/14

    Abstract: A module for rewriting application code as a failure-atomic transaction is disclosed. An application delineates a code fragment that is to become a failure-atomic transaction by writing a tx_begin( ) and tx_end( ) functions into its code. A module detects the tx_begin( ) and tx_end( ) functions and rewrites the code fragment as a failure-atomic transaction. The rewritten code is then available to be executed by the application. The rewritten code stores values and locations of stores to persistent memory locations so that the transaction can be either undone or redone in the case of an application error or a power failure. If the transaction is an undo type of transaction, the application can be rolled back to a state prior to the failure. If the transaction is a redo type of transaction, the application can be advanced to a correct state after the error.

    Smart prefetching for remote memory
    5.
    发明授权
    Smart prefetching for remote memory 有权

    公开(公告)号：US11442865B1

    公开(公告)日：2022-09-13

    申请号：US17367078

    申请日：2021-07-02

    Applicant: VMware, Inc.

    Inventor： Irina Calciu ,  Andreas Nowatzyk ,  Isam Wadih Akkawi ,  Venkata Subhash Reddy Peddamallu ,  Pratap Subrahmanyam

    IPC: G06F12/0862

    Abstract: A method of prefetching memory pages from remote memory includes detecting that a cache-line access made by a processor executing an application program is an access to a cache line containing page table data of the application program, identifying data pages that are referenced by the page table data, initiating a fetch of a data page, which is one of the identified data pages, and starting a timer. If the fetch completes prior to expiration of the timer, the data page is stored in a local memory. On the other hand, if the fetch does not complete prior to expiration of timer, a presence bit of the data page in the page table data is set to indicate that the data page is not present.

    Coherence-based attack detection
    8.
    发明授权
    Coherence-based attack detection 有权

    公开(公告)号：US12147528B2

    公开(公告)日：2024-11-19

    申请号：US17383342

    申请日：2021-07-22

    Applicant: VMware, Inc.

    Inventor： Irina Calciu ,  Andreas Nowatzyk ,  Pratap Subrahmanyam

    IPC: G06F21/52 ,  G06F9/455 ,  G06F12/0815 ,  G06F12/0891 ,  G06F21/55

    Abstract: While an application or a virtual machine (VM) is running, a device tracks accesses to cache lines to detect access patterns that indicate security attacks, such as cache-based side channel attacks or row hammer attacks. To enable the device to detect accesses to cache lines, the device is connected to processors via a coherence interconnect, and the application/VM data is stored in a local memory of the device. The device collects the cache lines of the application/VM data that are accessed while the application/VM is running into a buffer and the buffer is analyzed for access patterns that indicate security attacks.

    Cache line persistence indicator for non-volatile memory using coherence states
    9.
    发明授权
    Cache line persistence indicator for non-volatile memory using coherence states 有权

    公开(公告)号：US11221767B2

    公开(公告)日：2022-01-11

    申请号：US15785214

    申请日：2017-10-16

    Applicant: VMware, Inc.

    Inventor： Irina Calciu ,  Aasheesh Kolli

    IPC: G06F3/06 ,  G06F12/128 ,  G06F12/0871 ,  G06F12/0811

    Abstract: The disclosure provides an approach for testing if a cache line of a cache has been flushed to non-volatile memory (NVM). The approach generally includes reading, by a central processing unit (CPU), data from the NVM. The approach further includes storing, by the CPU, a copy of the data in the cache as a cache line. The approach further includes modifying, by the CPU, at least a portion of the copy of the data in the cache. The approach further includes requesting, by the CPU, the cache line be flushed to the NVM. The approach further includes performing, by the CPU, one or more instructions in parallel to the cache line being flushed to the NVM. The approach further includes requesting, by the CPU, a state of the cache line and determining if the cache line has been persisted in the NVM based on the state of the cache line.

    Failure-atomic logging for persistent memory systems with cache-coherent FPGAs
    10.
    发明授权
    Failure-atomic logging for persistent memory systems with cache-coherent FPGAs 有权

    公开(公告)号：US11068400B2

    公开(公告)日：2021-07-20

    申请号：US16256571

    申请日：2019-01-24

    Applicant: VMware, Inc.

    Inventor： Aasheesh Kolli ,  Irina Calciu ,  Jayneel Gandhi ,  Pratap Subrahmanyam

    IPC: G06F12/0831 ,  G06F12/109 ,  G06F9/50 ,  G06F11/07 ,  G06F12/0817

    Abstract: Disclosed is a technique in which an application can record changes it makes to physical memory. In the technique, the application specifies a virtual memory region which is converted to a plurality of cache lines, each of which is monitored for changes by a device connected to a coherence interconnect coupled to the processor caches. The application sends a start signal to start the logging process and an end signal to stop the process. During the logging process, when a change occurs to one of the cache lines, an undo entry corresponding to the change is created and entered into a transaction log residing in persistent memory. The transaction log containing the undo entries makes the set of changes recorded in the transaction log atomic. If a failure occurs, the recorded changes can be undone as if they never occurred.

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