利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

7 条记录 (耗时 0.028 秒)

    Partially decoded register renamer
    1.
    发明授权
    Partially decoded register renamer 有权
    部分解码寄存器重命名

    公开(公告)号：US07373486B2

    公开(公告)日：2008-05-13

    申请号：US11214193

    申请日：2005-08-29

    申请人： Wei-Han Lien ,  John K Yong ,  Shyam Sundar ,  Rajat Goel

    发明人： Wei-Han Lien ,  John K Yong ,  Shyam Sundar ,  Rajat Goel

    IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

    CPC分类号： G06F9/3836 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3861

    摘要： In one embodiment, a renamer comprises a plurality of storage locations and compare circuitry. Each storage location is assigned to a respective renameable resource and is configured to store an identifier corresponding to a youngest instruction operation that writes the respective renameable resource. Coupled to receive an input representing one or more retiring instruction identifiers corresponding to instruction operations that are being retired, the compare circuitry is configured to detect a match between at least a first identifier in a first storage location and one of the retiring identifiers. An encoded form of the identifiers is logically divided into a plurality of fields, and the input comprises a first plurality of bit vectors. Each of the first plurality of bit vectors corresponds to a respective field and includes a bit position for each possible value of the respective field.

    摘要翻译： 在一个实施例中，重新映射器包括多个存储位置和比较电路。 每个存储位置被分配给相应的可重命名资源，并且被配置为存储对应于写入相应可重命名资源的最小指令操作的标识符。 耦合以接收表示与正在退休的指令操作相对应的一个或多个退休指令标识符的输入，所述比较电路被配置为检测第一存储位置中的至少第一标识符与退出标识符之一的匹配。 标识符的编码形式在逻辑上被划分为多个字段，并且输入包括第一多个比特向量。 第一多个位向量中的每一个对应于相应的场，并且包括相应场的每个可能值的比特位置。

    Partially decoded register renamer
    2.
    发明申请
    Partially decoded register renamer 有权
    部分解码寄存器重命名

    公开(公告)号：US20070050602A1

    公开(公告)日：2007-03-01

    申请号：US11214193

    申请日：2005-08-29

    申请人： Wei-Han Lien ,  John Yong ,  Shyam Sundar ,  Rajat Goel

    发明人： Wei-Han Lien ,  John Yong ,  Shyam Sundar ,  Rajat Goel

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3836 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3861

    摘要： In one embodiment, a renamer comprises a plurality of storage locations and compare circuitry. Each storage location is assigned to a respective renameable resource and is configured to store an identifier corresponding to a youngest instruction operation that writes the respective renameable resource. Coupled to receive an input representing one or more retiring instruction identifiers corresponding to instruction operations that are being retired, the compare circuitry is configured to detect a match between at least a first identifier in a first storage location and one of the retiring identifiers. An encoded form of the identifiers is logically divided into a plurality of fields, and the input comprises a first plurality of bit vectors. Each of the first plurality of bit vectors corresponds to a respective field and includes a bit position for each possible value of the respective field.

    摘要翻译： 在一个实施例中，重新映射器包括多个存储位置和比较电路。 每个存储位置被分配给相应的可重命名资源，并且被配置为存储对应于写入相应可重命名资源的最小指令操作的标识符。 耦合以接收表示与正在退休的指令操作相对应的一个或多个退休指令标识符的输入，所述比较电路被配置为检测第一存储位置中的至少第一标识符与退出标识符之一的匹配。 标识符的编码形式在逻辑上被划分为多个字段，并且输入包括第一多个比特向量。 第一多个位向量中的每一个对应于相应的场，并且包括相应场的每个可能值的比特位置。

    Training Decode Unit for Previously-Detected Instruction Type
    3.
    发明申请
    Training Decode Unit for Previously-Detected Instruction Type 审中-公开
    以前检测到的指令类型的训练解码单元

    公开(公告)号：US20120079249A1

    公开(公告)日：2012-03-29

    申请号：US12892438

    申请日：2010-09-28

    申请人： Wei-Han Lien ,  Ian D. Kountanis ,  Shyam Sundar

    发明人： Wei-Han Lien ,  Ian D. Kountanis ,  Shyam Sundar

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3822 ,  G06F9/30145

    摘要： In an embodiment, a decode unit includes multiple decoders configured to decode different types of instructions. One or more of the decoders may be complex decoders, and the decode unit may disable the complex decoders if an instruction of the corresponding type is not being decoded. In an embodiment, the decode unit may disable the complex decoders by data-gating the instruction into the decoder. The decode unit may also include a control unit that is configured to detect instructions of the type decoded by the complex decoders, and to enable the complex decoders and redirect the fetching in response to the detection. The decode unit may also record an indication of the instruction (e.g. the program counter address (PC) of the instruction) to more rapidly detect the instruction and prevent a redirect in subsequent fetches.

    摘要翻译： 在一个实施例中，解码单元包括被配置为解码不同类型的指令的多个解码器。 一个或多个解码器可以是复杂解码器，并且如果对应类型的指令未被解码，则解码单元可以禁用复数解码器。 在一个实施例中，解码单元可以通过将解码器的指令进行数据门控来禁用复数解码器。 解码单元还可以包括控制单元，其被配置为检测由复合解码器解码的类型的指令，并且使得复制解码器能够响应于检测而重定向该取出。 解码单元还可以记录指令的指示（例如，指令的程序计数器地址（PC）），以更快速地检测指令并防止后续读取中的重定向。

    Method and apparatus for signal electromigration analysis
    6.
    发明授权
    Method and apparatus for signal electromigration analysis 有权
    用于信号电迁移分析的方法和装置

    公开(公告)号：US06954914B2

    公开(公告)日：2005-10-11

    申请号：US10395436

    申请日：2003-03-24

    申请人： Shyam Sundar ,  Aveek Sarkar ,  Peter F. Lai ,  Rambabu Pyapali ,  Teong Ming Cheah

    发明人： Shyam Sundar ,  Aveek Sarkar ,  Peter F. Lai ,  Rambabu Pyapali ,  Teong Ming Cheah

    IPC分类号： G06F9/45 ,  G06F17/50

    CPC分类号： G06F17/5036

    摘要： The present application describes various embodiments of a method and an apparatus for determining electromigration risks for signal nets in integrated circuits. A model for each one of the global nets connecting various circuit blocks in an integrated circuit is created using circuit blocks' timing model and detailed standard parasitic format representation (DSPF) of each global net. The final layout of the integrated circuit is not necessary to determine the electromigration risks. The models can be generated during the early stages of the design cycle once the DSPF of the global nets is available.

    摘要翻译： 本申请描述了用于确定集成电路中的信号网的电迁移风险的方法和装置的各种实施例。 使用电路块的定时模型和每个全局网络的详细标准寄生格式表示（DSPF），创建连接集成电路中的各种电路块的每个全球网络的模型。 集成电路的最终布局不需要确定电迁移风险。 一旦全球网络的DSPF可用，这些模型可以在设计周期的早期阶段生成。

    Method and apparatus for power consumption analysis in global nets
    7.
    发明授权
    Method and apparatus for power consumption analysis in global nets 有权
    全球网络功耗分析方法与装置

    公开(公告)号：US07007256B2

    公开(公告)日：2006-02-28

    申请号：US10383092

    申请日：2003-03-06

    申请人： Aveek Sarkar ,  Shyam Sundar ,  Peter F. Lai ,  Rambabu Pyapali

    发明人： Aveek Sarkar ,  Shyam Sundar ,  Peter F. Lai ,  Rambabu Pyapali

    IPC分类号： G06F9/45 ,  G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5022 ,  G06F17/505 ,  G06F2217/78

    摘要： The present invention describes a method and an apparatus for determining switching power consumption of global devices (e.g., repeaters, flops or the like) in an integrated circuit design during high-level design phase after the global routing for the integrated circuit is available. The clock cycle is divided into various timing intervals and the timing reports are generated for each cycle to determine a time-domain staggered distribution of each device's switching activity within a given timing interval. Each device's switching activity is analyzed within the given timing interval (or segment thereof). The power consumption is determined for each device that switches in the given timing interval.

    摘要翻译： 本发明描述了在集成电路的全局路由可用之后在高级设计阶段期间在集成电路设计中确定全局设备（例如，中继器，触发器等）的开关功耗的方法和装置。 时钟周期分为不同的定时间隔，并为每个周期生成定时报告，以确定给定时间间隔内每个设备的交换活动的时域交错分布。 在给定的时间间隔（或其段）内分析每个设备的切换活动。 确定在给定时间间隔内切换的每个设备的功耗。