公开(公告)号：US20240224542A1

公开(公告)日：2024-07-04

申请号：US18090216

申请日：2022-12-28

Applicant: XILINX, INC.

Inventor： Zachary BLAIR ,  Gabriel LOH ,  Paul HARTKE

IPC: H10B80/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: H10B80/00 ,  H01L23/5223 ,  H01L23/5286

Abstract: A DRAM fabrication process for producing a semiconductor die adapted for having the ability to be both a hybrid memory and power supply capacitance. DRAM arrays on a semiconductor die may be individually selected to function as either a memory or as supplemental capacitance on a power distribution network serving circuits on one or more semiconductor dice in a three-dimensional active-on-active (AoA) stacked semiconductor die package configuration. Defective DRAM array trench capacitors can be repurposed to serve as supplemental capacitance on a power distribution network. DRAM array trench capacitors can be dynamically reassigned as supplemental capacitance when power supply monitors sense that additional power supply capacitance is needed.