公开(公告)号：US20240224542A1

公开(公告)日：2024-07-04

申请号：US18090216

申请日：2022-12-28

Applicant: XILINX, INC.

Inventor： Zachary BLAIR ,  Gabriel LOH ,  Paul HARTKE

IPC: H10B80/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: H10B80/00 ,  H01L23/5223 ,  H01L23/5286

Abstract: A DRAM fabrication process for producing a semiconductor die adapted for having the ability to be both a hybrid memory and power supply capacitance. DRAM arrays on a semiconductor die may be individually selected to function as either a memory or as supplemental capacitance on a power distribution network serving circuits on one or more semiconductor dice in a three-dimensional active-on-active (AoA) stacked semiconductor die package configuration. Defective DRAM array trench capacitors can be repurposed to serve as supplemental capacitance on a power distribution network. DRAM array trench capacitors can be dynamically reassigned as supplemental capacitance when power supply monitors sense that additional power supply capacitance is needed.

公开(公告)号：US20250150520A1

公开(公告)日：2025-05-08

申请号：US19015963

申请日：2025-01-10

Applicant: XILINX, INC.

Inventor： Edward RICHTER ,  Paul HARTKE ,  Philip JAMES-ROXBY

IPC: H04L69/08 ,  G06F3/06 ,  G06F5/00 ,  H03M7/24 ,  H04L1/00

Abstract: A computing node for a computing system includes a processor, conversion circuitry, and routing circuitry. The processor generates a data signal based on a function of an application executed by the computing system. The data signal has a first precision format and a first sparse representation. The conversion circuitry receives the data signal from the processor and generate a converted data signal by at least one of converting the first precision format to a second precision format and converting the first sparse representation to a second sparse representation. The routing circuitry transmits the converted data signal to switch circuitry of the computing system.

公开(公告)号：US20240195889A1

公开(公告)日：2024-06-13

申请号：US18080602

申请日：2022-12-13

Applicant: XILINX, INC.

Inventor： Edward RICHTER ,  Paul HARTKE ,  Philip JAMES-ROXBY

IPC: H04L69/08

CPC classification number: H04L69/08

Abstract: A computing node for a computing system includes a processor, conversion circuitry, and routing circuitry. The processor generates a data signal based on a function of an application executed by the computing system. The data signal has a first precision format and a first sparse representation. The conversion circuitry receives the data signal from the processor and generate a converted data signal by at least one of converting the first precision format to a second precision format and converting the first sparse representation to a second sparse representation. The routing circuitry transmits the converted data signal to switch circuitry of the computing system.