公开(公告)号：US20240143891A1

公开(公告)日：2024-05-02

申请号：US17979649

申请日：2022-11-02

Applicant: XILINX, INC.

Inventor： Surya Rajendra Swamy Saranam CHONGALA ,  Nikhil Arun DHUME ,  Krishnan SRINIVASAN ,  Dinesh D. GAITONDE

IPC: G06F30/3953

CPC classification number: G06F30/3953

Abstract: Embodiments herein describe a network on chip (NoC) that implements multi-path routing (MPR) between an ingress logic block and an egress logic block. The multiple paths between the ingress and egress logic blocks can be assigned different alias destination IDs corresponding to the same destination ID. The NoC can use the alias destination IDs to route the packets along the different paths through interconnected switches in the NoC.