公开(公告)号：US20240143891A1

公开(公告)日：2024-05-02

申请号：US17979649

申请日：2022-11-02

Applicant: XILINX, INC.

Inventor： Surya Rajendra Swamy Saranam CHONGALA ,  Nikhil Arun DHUME ,  Krishnan SRINIVASAN ,  Dinesh D. GAITONDE

IPC: G06F30/3953

CPC classification number: G06F30/3953

Abstract: Embodiments herein describe a network on chip (NoC) that implements multi-path routing (MPR) between an ingress logic block and an egress logic block. The multiple paths between the ingress and egress logic blocks can be assigned different alias destination IDs corresponding to the same destination ID. The NoC can use the alias destination IDs to route the packets along the different paths through interconnected switches in the NoC.

公开(公告)号：US20230036531A1

公开(公告)日：2023-02-02

申请号：US17389272

申请日：2021-07-29

Applicant: XILINX, INC.

Inventor： Krishnan SRINIVASAN ,  Shishir KUMAR ,  Sagheer AHMAD ,  Abbas MORSHED ,  Aman GUPTA

IPC: G06F3/06

Abstract: Some examples described herein provide a buffer memory pool circuitry that comprises a plurality of buffer memory circuits that store an entry identifier, a payload portion, and a next-entry pointer. The buffer memory pool circuitry further comprises a processor configured to identify an allocation request for a first virtual channel associated with a sequence of buffer memory circuits and comprising a start pointer identifying an initial buffer memory circuit. The processor is further configured to program the first virtual channel circuit based on setting the start pointer for the first virtual channel circuit to be equal to the entry identifier of the initial buffer memory circuit. The processor is also configured to monitor usage. A length of the sequence of buffer memory circuits of the first virtual channel circuit is defined by a start pointer for a second virtual channel circuit subsequent to the first virtual channel circuit.

公开(公告)号：US20240176758A1

公开(公告)日：2024-05-30

申请号：US18432847

申请日：2024-02-05

Applicant: XILINX, INC.

Inventor： Krishnan SRINIVASAN ,  Ygal ARBEL ,  Sagheer AHMAD

IPC: G06F13/42

CPC classification number: G06F13/4282 ,  G06F2213/0016

Abstract: Systems, methods, and apparatuses are described that enable IC architectures to enable a single anchor to connect to and accept a variety of chiplets at any port by way of a programming model that enables the anchor or chiplet to dynamically adapt to configurations, requirements, or aspects of any coupled component and provide an interface for the coupled components.

公开(公告)号：US20240111704A1

公开(公告)日：2024-04-04

申请号：US17959903

申请日：2022-10-04

Applicant: XILINX, INC.

Inventor： Krishnan SRINIVASAN ,  Abbas MORSHED ,  Sagheer AHMAD

IPC: G06F13/40

CPC classification number: G06F13/4059 ,  G06F13/4022

Abstract: Embodiments herein describe a NoC where its internal switches have buffers with pods that can be assigned to different virtual channels. A subset of the pods in a buffer can be grouped together to form a VC. In this manner, different pod groups in a buffer can be assigned to different VCs (or to different types of NoC data units), where VCs that transmit wider data units can be assigned more pods than VCs that transmit narrower data units.

公开(公告)号：US20240111693A1

公开(公告)日：2024-04-04

申请号：US17957418

申请日：2022-09-30

Applicant: XILINX, INC.

Inventor： Krishnan SRINIVASAN ,  Ygal ARBEL ,  Sagheer AHMAD ,  Sarosh I. AZAD ,  Pramod BHARDWAJ ,  Yanran CHEN ,  James MURRAY

IPC: G06F13/16 ,  G06F11/07

CPC classification number: G06F13/1631 ,  G06F11/0772 ,  G06F13/1668

Abstract: Techniques to provide transaction redundancy in an IC include receiving an original memory access request directed to a first memory aperture, constructing a redundant memory access directed to a second memory aperture, and selectively returning a response of the first or second memory aperture to an originator based on contents of the responses. For a write operation, if acknowledgement indicators of the responses indicate success, a response is returned to the originator. For a read operation, if acknowledgement indicators of the responses indicate success and data returned in the response match one another, a response is returned to the originator. If the acknowledgement indicators indicate success, but the data does not match, a retry of the original and redundant read requests is initiated. If any of the acknowledgement indicators do not indicate success, an error is declared. In a mixed-criticality embodiment, the redundant memory access request may be constructed selectively.

公开(公告)号：US20230244628A1

公开(公告)日：2023-08-03

申请号：US17589633

申请日：2022-01-31

Applicant: XILINX, INC.

Inventor： Krishnan SRINIVASAN ,  Sagheer AHMAD ,  Ygal ARBEL ,  Millind MITTAL

IPC: G06F13/42 ,  G06F13/38 ,  G06F13/40

CPC classification number: G06F13/42 ,  G06F13/382 ,  G06F13/4063

Abstract: Embodiments herein describe using an adaptive chip-to-chip (C2C) interface to interconnect two chips, wherein the adaptive C2C interface includes circuitry for performing multiple different C2C protocols to communicate with the other chip. One or both of the chips in the C2C connection can include the adaptive C2C interface. During boot time, the adaptive C2C interface is configured to perform one of the different C2C protocols. During runtime, the chip then uses the selected C2C protocol to communicate with the other chip in the C2C connection.

公开(公告)号：US20250077116A1

公开(公告)日：2025-03-06

申请号：US18241142

申请日：2023-08-31

Applicant: XILINX, INC.

Inventor： Ygal ARBEL ,  Krishnan SRINIVASAN

IPC: G06F3/06

Abstract: An integrated circuit device includes interconnect circuitry. The interconnect circuitry includes interleaving switch circuitries, network switch circuitries, and crossbar circuitries. The interleaving switch circuitries are coupled to requester devices. A first interleaving switch circuitry includes first ports. The first interleaving switch circuitry receives a first memory command, and outputs the first memory command via first communication lanes connected to a first port based on a memory address of the first memory command. The network switch circuitries are connected to the interleaving switch circuitries. A first network switch circuitry is connected to the first communication lanes and route the first memory command along the first communication lanes based on the memory address. A first crossbar circuitry of the crossbar circuitries receives the first memory command from the first communication lanes, and outputs the first memory command to a first memory device of the memory devices associated with the memory

公开(公告)号：US20250030500A1

公开(公告)日：2025-01-23

申请号：US18223517

申请日：2023-07-18

Applicant: XILINX, INC.

Inventor： Millind MITTAL ,  Krishnan SRINIVASAN ,  Kenneth MA

IPC: H04L1/00 ,  H04L49/9005

Abstract: Some examples described herein provide for interconnect in chiplet systems, for example system-level techniques for error correction in chip-to-chip interfaces. In an example, a method of error correction includes receiving, at a first chiplet, a data message via a set of interconnect, and transmitting a first control message that requests retransmission of the data message based on detecting an error associated with receiving the data message. The method also includes transmitting one or more instances of a second control message that indicates an idle operation at the first chiplet until the first chiplet receives a third control message that triggers an end of a retransmission mode. The method also includes transmitting a fourth control message frame indicating the end of the retransmission mode, and receiving a retransmission of the data message from the second chiplet.

公开(公告)号：US20230141709A1

公开(公告)日：2023-05-11

申请号：US17551132

申请日：2021-12-14

Applicant: XILINX, INC.

Inventor： Krishnan SRINIVASAN ,  Ygal ARBEL ,  Sagheer AHMAD

IPC: G06F13/42

CPC classification number: G06F13/4282 ,  G06F2213/0016

Abstract: Systems, methods, and apparatuses are described that enable IC architectures to enable a single anchor to connect to and accept a variety of chiplets at any port by way of a programming model that enables the anchor or chiplet to dynamically adapt to configurations, requirements, or aspects of any coupled component and provide an interface for the coupled components.

公开(公告)号：US20250080716A1

公开(公告)日：2025-03-06

申请号：US18241161

申请日：2023-08-31

Applicant: XILINX, INC.

Inventor： Yanran CHEN ,  Roger MAY ,  Sagheer AHMAD ,  Qingyi SHENG ,  Krishnan SRINIVASAN ,  Vishal SAGAR ,  Pramod BHARDWAJ ,  Yashu GOSAIN

IPC: H04N17/00

Abstract: Some examples described herein provide for display image data reliability and safety, for example end-to-end safety methods, apparatuses, and systems for display systems. One example includes a method, including replacing video frames from input video streams with a set of test frames. The method further includes generating an alpha-blended video stream based on the set of test frames and the input video streams. The method further includes generating and inserting cyclic redundancy check (CRC) information for the set of test frames into secondary data packets associated with the alpha-blended video stream. The method further includes processing the set of test frames and video frames by a display controller to generate an output video stream. The method further includes performing an error detection procedure for the set of test frames using the CRC information to detect an error associated with the set of video frames.