Core cavity noise isolation structure for use in chip packages

    公开(公告)号:US11688675B1

    公开(公告)日:2023-06-27

    申请号:US17315229

    申请日:2021-05-07

    Applicant: XILINX, INC.

    Abstract: Various noise isolation structures and methods for fabricating the same are presented. In one example, a substrate for chip package is provided. The substrate includes a core region, top build-up layers and bottom build-up layers. The top build-up layers are formed on a first side of the core region and the bottom build-up layers are formed on a second side of the core region that is opposite the first side. Routing circuitry formed in the bottom build-up layers is coupled to routing circuitry formed in the top build-up layers by vias formed through the core region. A void is formed in the bottom build-up layers. The void is configured as a noise isolation structure. The void has a sectional area that is different in at least two different distances from the core region.

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