公开(公告)号：US20240333270A1

公开(公告)日：2024-10-03

申请号：US18128945

申请日：2023-03-30

Applicant: XILINX, INC.

Inventor： Riyas Noorudeen REMLA ,  Showi-Min SHEN

IPC: H03K5/01

CPC classification number: H03K5/01 ,  H03K2005/00078 ,  H03K2005/00286

Abstract: Receiver circuitry for mitigating effects associated with the phase differences between a capture clock signal and the receipt of a data signal includes first data path circuitry, second data path circuitry, and phase alignment circuitry. The first data path circuitry receives a first data signal based on a capture clock signal. The second data path circuitry receives a second data signal based on the capture clock signal. The phase alignment circuitry adjusts the phase of a first launch clock signal and a second launch clock signal based on a first clock slip signal and a second clock slip signal, respectively. The phase alignment circuitry adjusts a phase of the capture clock signal relative to one of the first and the second launch clock signals based on a first adjustment value associated with the first data path circuitry and a second adjustment value associated with the second data path circuitry.