公开(公告)号：US20220407676A1

公开(公告)日：2022-12-22

申请号：US17351028

申请日：2021-06-17

Applicant: XILINX, INC.

Inventor： Wenfeng ZHANG ,  Zhaoyin Daniel WU ,  Parag UPADHYAYA

IPC: H04L7/00 ,  H04B1/16

Abstract: In one example, receiver circuitry for a communication system comprises signal processing circuitry configured to receive a data signal and generate a processed data signal, and error slicer circuitry. The error slicer circuitry is coupled to the output of the signal processing circuitry, and configured to receive the processed data signal. The error slicer circuitry comprises a first error slicer configured to receive a clock signal, and output a first error signal based on a first state of the clock signal and processed data signal. The first error slicer is further configured to output a second error signal based on a second state of the clock signal and the processed data signal.

公开(公告)号：US20230050659A1

公开(公告)日：2023-02-16

申请号：US17398675

申请日：2021-08-10

Applicant: XILINX, INC.

Inventor： Wenfeng ZHANG ,  Parag UPADHYAYA

IPC: H03K5/003 ,  H04B1/16 ,  H04L27/32 ,  H03K3/037

Abstract: Receiver circuitry for a communication system includes signal processing circuitry, voltage digital-to-analog converter (DAC) circuitry, and slicer circuitry. The signal processing circuitry receives a data signal and generate a processed data signal. The voltage DAC circuitry generates a first threshold reference voltage. The slicer circuitry is coupled to an output of the signal processing circuitry. The slicer circuitry includes a capture flip-flop (CapFF) circuit that receives the processed data signal and the first threshold reference voltage. The CapFF circuit further generates a first data signal. The first CapFF circuit includes a first offset compensation circuit that adjusts a parasitic capacitance of the first CapFF circuit.