公开(公告)号：US09235498B1

公开(公告)日：2016-01-12

申请号：US13908160

申请日：2013-06-03

Applicant: Xilinx, Inc.

Inventor： Jay Southard ,  Krishna Garlapati ,  Elliott Delaye ,  Ashish Sirasao ,  Bing Tian

IPC: G06F12/00

CPC classification number: G11C19/28 ,  G06F17/5054 ,  G11C7/1006 ,  G11C7/1039 ,  H03K5/131 ,  H03K19/1737

Abstract: A circuit for enabling a modification of an input data stream is described. The circuit comprises a first plurality of registers coupled in series; an input register of the first plurality of registers coupled to receive the input data stream; an output register of the first plurality of registers positioned at an end of the first plurality of registers; and a control circuit enabling a data value which is independent of the input data stream to be generated as an output of the circuit at a predetermined time.

Abstract translation: 描述了能够修改输入数据流的电路。 电路包括串联耦合的第一多个寄存器; 耦合以接收所述输入数据流的所述第一多个寄存器的输入寄存器; 所述第一多个寄存器的输出寄存器位于所述第一多个寄存器的一端; 以及控制电路，使得能够在预定时间内产生独立于输入数据流的数据值作为电路的输出。