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    Dynamic power reduction in circuit designs and circuits
    1.
    发明授权
    Dynamic power reduction in circuit designs and circuits 有权

    公开(公告)号：US10387600B2

    公开(公告)日：2019-08-20

    申请号：US15266827

    申请日：2016-09-15

    Applicant: Xilinx, Inc.

    Inventor： Chaithanya Dudha ,  Krishna Garlapati

    IPC: G06F17/50 ,  G06F1/32

    Abstract: Reducing dynamic power consumption for a circuit can include analyzing, using a processor, a netlist specifying the circuit to determine a block of combinatorial circuitry in a first signal path with at least a threshold amount of switching activity and detecting, using the processor, a second signal path coupled to the block of combinatorial circuitry by a sequential circuit element. The second signal path has a delay that meets a target signal path requirement. Using the processor, the netlist can be modified by subdividing the block of combinatorial circuitry into at least a first portion and a second portion and moving one of the portions from the first signal path to the second signal path, wherein the moving separates the first portion from the second portion by the sequential circuit element.

    Compact and efficient circuit implementation of dynamic ranges in hardware description languages
    4.
    发明授权
    Compact and efficient circuit implementation of dynamic ranges in hardware description languages 有权
    硬件描述语言中动态范围的紧凑高效电路实现

    公开(公告)号：US09268891B1

    公开(公告)日：2016-02-23

    申请号：US14535267

    申请日：2014-11-06

    Applicant: Xilinx, Inc.

    Inventor： Krishna Garlapati ,  Elliott Delaye ,  Ashish Sirasao ,  Bing Tian

    IPC: G06F17/50 ,  G01R31/317 ,  G01R31/3177

    CPC classification number: G06F17/5045 ,  G01R31/31703 ,  G01R31/3177

    Abstract: Compiling a circuit design includes receiving the circuit design specified in a hardware description language, detecting, using a processor, a slice of a vector within the circuit design, and determining that the slice is defined by a left slice boundary variable and a right slice boundary variable. A hardware description is generated from the circuit design using the processor by including a first shifter circuit receiving the left slice boundary variable as an input signal, a second shifter circuit receiving the right slice boundary variable as an input signal, a control signal generator coupled to the first and second shifter circuits, and an output stage. The output stage, responsive to a control signal dependent upon an output from the first shifter circuit and an output from second shifter circuit, generates an output signal including newly received values from a data signal only for bit locations of the output signal corresponding to the slice.

    Abstract translation: 编译电路设计包括接收以硬件描述语言指定的电路设计，使用处理器检测电路设计内的向量片，以及确定该片由左片边界变量和右片段边界定义 变量。 通过包括接收左边界边界变量的第一移位器电路作为输入信号，接收右边界边界变量的第二移位器电路作为输入信号，通过使用处理器的电路设计产生硬件描述，控制信号发生器耦合到 第一和第二移位器电路以及输出级。 响应于取决于第一移位器电路的输出的控制信号和来自第二移位器电路的输出的输出级产生包括仅针对对应于切片的输出信号的位位置的来自数据信号的新接收值的输出信号 。

    Selecting predefined circuit implementations in a circuit design system
    5.
    发明授权
    Selecting predefined circuit implementations in a circuit design system 有权
    在电路设计系统中选择预定义的电路实现

    公开(公告)号：US09460253B1

    公开(公告)日：2016-10-04

    申请号：US14482945

    申请日：2014-09-10

    Applicant: Xilinx, Inc.

    Inventor： Elliott Delaye ,  Ashish Sirasao ,  Krishna Garlapati ,  Bing Tian

    IPC: G06F17/50

    CPC classification number: G06F17/505 ,  G06F17/5054 ,  G06F2217/14 ,  G06F2217/64 ,  G06F2217/66

    Abstract: In an example, a method of processing a circuit design includes: determining a first partition in a description of the circuit design having a hierarchy of design objects, the first partition including at least one design object in the hierarchy of design objects; generating a signature for the first partition; querying a database with the signature of the first partition to identify a plurality of predefined implementations of the first partition; and generating an implementation of the circuit design for a target integrated circuit (IC) based on a selected predefined implementation of the plurality of predefined implementations for the first partition.

    Abstract translation: 在一个示例中，一种处理电路设计的方法包括：在具有设计对象层级的电路设计的描述中确定第一分区，第一分区包括设计对象层级中的至少一个设计对象; 生成第一分区的签名; 用第一分区的签名查询数据库以识别第一分区的多个预定义的实现; 以及基于用于所述第一分区的所述多个预定义实现的所选择的预定义实现来生成用于目标集成电路（IC）的电路设计的实现。

    Object identification in an electronic circuit design
    6.
    发明授权
    Object identification in an electronic circuit design 有权
    电子电路设计中的物体识别

    公开(公告)号：US08667436B1

    公开(公告)日：2014-03-04

    申请号：US13782123

    申请日：2013-03-01

    Applicant: Xilinx, Inc.

    Inventor： Krishna Garlapati ,  Elliot Delaye ,  Ashish Sirasao

    IPC: G06F17/50

    CPC classification number: G06F17/505 ,  G06F17/5022 ,  G06F17/5045

    Abstract: The disclosure describes approaches for processing a circuit design. For each object of a plurality of objects of the circuit design, a respective key is generated as a function of a plurality of configuration parameter values of the object. Each object is renamed with a unique name that includes the key. A netlist of the circuit design is generated using the unique names and keys of the objects.

    Abstract translation: 本公开描述了用于处理电路设计的方法。 对于电路设计的多个对象的每个对象，根据对象的多个配置参数值生成相应的键。 每个对象都使用包含密钥的唯一名称进行重命名。 使用对象的唯一名称和密钥生成电路设计的网表。

    Implementing a circuit design with re-convergence
    8.
    发明授权
    Implementing a circuit design with re-convergence 有权

    公开(公告)号：US10990736B1

    公开(公告)日：2021-04-27

    申请号：US16821465

    申请日：2020-03-17

    Applicant: Xilinx, Inc.

    Inventor： Chaithanya Dudha ,  Satyaprakash Pareek ,  Krishna Garlapati ,  Ashish Sirasao

    IPC: G06F30/30 ,  G06F30/337 ,  G06F30/327 ,  G03F1/70 ,  G06F30/31 ,  G06F119/12

    Abstract: Implementing a circuit design can include detecting, using computer hardware, a re-convergent section of a circuit design, masking, using the computer hardware, a sequential circuit element of the re-convergent section located between a start and an end of the re-convergent section, and performing, using the computer hardware, an optimization operation on combinatorial logic of the re-convergent section to create optimized combinatorial logic. Using the computer hardware, the optimized combinatorial logic of the re-convergent section can be mapped. Further, the re-convergent section can be modified subsequent to the mapping to match timing of the re-convergent section prior to the masking.

    DYNAMIC POWER REDUCTION IN CIRCUIT DESIGNS AND CIRCUITS
    9.
    发明申请
    DYNAMIC POWER REDUCTION IN CIRCUIT DESIGNS AND CIRCUITS 审中-公开

    公开(公告)号：US20180075172A1

    公开(公告)日：2018-03-15

    申请号：US15266827

    申请日：2016-09-15

    Applicant: Xilinx, Inc.

    Inventor： Chaithanya Dudha ,  Krishna Garlapati

    IPC: G06F17/50

    CPC classification number: G06F17/505 ,  G06F1/32 ,  G06F17/5045 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/78 ,  G06F2217/84

    Abstract: Reducing dynamic power consumption for a circuit can include analyzing, using a processor, a netlist specifying the circuit to determine a block of combinatorial circuitry in a first signal path with at least a threshold amount of switching activity and detecting, using the processor, a second signal path coupled to the block of combinatorial circuitry by a sequential circuit element. The second signal path has a delay that meets a target signal path requirement. Using the processor, the netlist can be modified by subdividing the block of combinatorial circuitry into at least a first portion and a second portion and moving one of the portions from the first signal path to the second signal path, wherein the moving separates the first portion from the second portion by the sequential circuit element.

    Circuits for and methods of enabling the modification of an input data stream
    10.
    发明授权
    Circuits for and methods of enabling the modification of an input data stream 有权
    用于启用输入数据流修改的电路和方法

    公开(公告)号：US09235498B1

    公开(公告)日：2016-01-12

    申请号：US13908160

    申请日：2013-06-03

    Applicant: Xilinx, Inc.

    Inventor： Jay Southard ,  Krishna Garlapati ,  Elliott Delaye ,  Ashish Sirasao ,  Bing Tian

    IPC: G06F12/00

    CPC classification number: G11C19/28 ,  G06F17/5054 ,  G11C7/1006 ,  G11C7/1039 ,  H03K5/131 ,  H03K19/1737

    Abstract: A circuit for enabling a modification of an input data stream is described. The circuit comprises a first plurality of registers coupled in series; an input register of the first plurality of registers coupled to receive the input data stream; an output register of the first plurality of registers positioned at an end of the first plurality of registers; and a control circuit enabling a data value which is independent of the input data stream to be generated as an output of the circuit at a predetermined time.

    Abstract translation: 描述了能够修改输入数据流的电路。 电路包括串联耦合的第一多个寄存器; 耦合以接收所述输入数据流的所述第一多个寄存器的输入寄存器; 所述第一多个寄存器的输出寄存器位于所述第一多个寄存器的一端; 以及控制电路，使得能够在预定时间内产生独立于输入数据流的数据值作为电路的输出。

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