公开(公告)号：US10107855B1

公开(公告)日：2018-10-23

申请号：US14536474

申请日：2014-11-07

Applicant: Xilinx, Inc.

Inventor： John D. Corbett ,  Steven E. McNeil

IPC: G01R31/28

Abstract: Apparatuses, systems, and methods for detecting changes to an IC are disclosed. In an example implementation, an apparatus includes an electromagnetic (EM) sensor. A high-resolution analog-to-digital converter (ADC) is configured to quantize a segment of the EM signal of an IC measured by the EM sensor. The quantized segment of the EM signal is unique to process-voltage-temperature (PVT) characteristics exhibited by the IC. The apparatus also includes a processing circuit configured to prompt the high-resolution ADC, via a control signal, to produce the quantized segment of the EM signal. The processing circuit determines a first signature from the quantized segment and retrieves a baseline signature corresponding to the IC from a data storage circuit. In response to the first signature being different from the baseline signature, the processing circuit indicates that a change to the IC is detected.

公开(公告)号：US09436786B1

公开(公告)日：2016-09-06

申请号：US14817521

申请日：2015-08-04

Applicant: Xilinx, Inc.

Inventor： John D. Corbett

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5054 ,  G06F17/5077 ,  G06F2217/84

Abstract: Methods and circuits for superclocked operation of a plurality of functionally-equivalent logic circuits are disclosed. One of the plurality of functionally-equivalent logic circuits is selected according to a selection algorithm. In response to selecting one of the plurality of functionally-equivalent logic circuits, superclocked operation of the selected one of the plurality of functionally-equivalent logic circuits is enabled. Superclocked operation of other ones of the plurality of functionally-equivalent logic circuits is disabled. The selected one of the plurality of functionally-equivalent logic circuits is used to process a portion of the input data set at the superclocked clock frequency.

Abstract translation: 公开了用于多个功能等效逻辑电路的超频操作的方法和电路。 根据选择算法来选择多个功能等效的逻辑电路中的一个。 响应于选择多个功能等效逻辑电路中的一个，使得多个功能等效逻辑电路中所选择的一个的超频操作成为可能。 多个功能等效逻辑电路中的其他功能等效逻辑电路的超级锁存操作被禁止。 多个功能等效逻辑电路中的所选择的一个用于处理以超频时钟频率设置的输入数据的一部分。