公开(公告)号：US11501142B1

公开(公告)日：2022-11-15

申请号：US16374451

申请日：2019-04-03

Applicant: Xilinx, Inc.

Inventor： Victor J. Wu ,  Poching Sun ,  Thomas A. Branca ,  Justin Thant Hsin Oo

IPC: G06N3/063 ,  G06F9/30 ,  G06F3/06 ,  G06F9/38

Abstract: A download dispatch circuit initiates download of an input tile of an input feature map in response to a source buffer of two or more source buffers being available for the input tile, and indicates that the input tile is available in response to completion of the download. An operation dispatch circuit initiates a neural network operation on the input tile in response to the input tile being available and a first destination buffer of two or more destination buffers being available for an output tile of an output feature map, and indicates that the output tile is available in response to completion of the neural network operation. An upload dispatch circuit initiates upload of the output tile to the output feature map in response to the output tile being available, and indicates that the first destination buffer is available in response to completion of the upload.