公开(公告)号：US11501142B1

公开(公告)日：2022-11-15

申请号：US16374451

申请日：2019-04-03

Applicant: Xilinx, Inc.

Inventor： Victor J. Wu ,  Poching Sun ,  Thomas A. Branca ,  Justin Thant Hsin Oo

IPC: G06N3/063 ,  G06F9/30 ,  G06F3/06 ,  G06F9/38

Abstract: A download dispatch circuit initiates download of an input tile of an input feature map in response to a source buffer of two or more source buffers being available for the input tile, and indicates that the input tile is available in response to completion of the download. An operation dispatch circuit initiates a neural network operation on the input tile in response to the input tile being available and a first destination buffer of two or more destination buffers being available for an output tile of an output feature map, and indicates that the output tile is available in response to completion of the neural network operation. An upload dispatch circuit initiates upload of the output tile to the output feature map in response to the output tile being available, and indicates that the first destination buffer is available in response to completion of the upload.

公开(公告)号：US10747534B1

公开(公告)日：2020-08-18

申请号：US16200336

申请日：2018-11-26

Applicant: Xilinx, Inc.

Inventor： Thomas B. Preusser ,  Thomas A. Branca

IPC: G06F7/499 ,  G06F9/30

Abstract: The embodiments herein describe techniques for monitoring guard bits in multi-result vectors generated by a first arithmetic unit in a chain and using side band logic to add or subtract offset values from guard bits in a second, subsequent arithmetic unit in the chain. In this manner, the guard bits can be adjusted on the fly (e.g., without interrupting or terminating the chain) to ensure the guard bits do not overflow. The side band logic can maintain a guard bits overflow value which is then combined with the output vector from the final arithmetic unit in the chain to compensate for adjusting the guard bits at the various arithmetic units in the chain. In this manner, the chain can have any desired length.

公开(公告)号：US10671388B1

公开(公告)日：2020-06-02

申请号：US16200313

申请日：2018-11-26

Applicant: Xilinx, Inc.

Inventor： Thomas B. Preusser ,  Thomas A. Branca

IPC: G06F7/499 ,  G06F9/30

Abstract: The embodiments herein describe handling overflow that occurs between different portions of a multi-result vector storing results from performing multiple operations in parallel. Rather than using guard bits to separate the various results in the multi-result vector, the embodiments herein describe using overflow monitors to detect and account for overflow that can occur in a multi-result vector that is passed in a chain of arithmetic units. Side band logic evaluates the LSBs in the operands for the reduced-precision operations to generate an expected value of performing the operation and compares the expected value to an actual value of the corresponding bits in the multi-result vector. If the expected and actual values match, then there was no overflow. However, if the values do not match, the side band logic updates the overflow value so that this overflow can be corrected once the final multi-result vector has been calculated.