公开(公告)号：US11704535B1

公开(公告)日：2023-07-18

申请号：US16415907

申请日：2019-05-17

Applicant: Xilinx, Inc.

Inventor： Kumar S. S. Vemuri ,  Mahesh S. Mahadurkar ,  Pavan K. Nadimpalli ,  Venkat Praveen K. Kancharlapalli

IPC: G06N3/04 ,  G06F3/06 ,  G06N3/063 ,  G06F5/16 ,  G06N3/02 ,  G06N3/06 ,  G06N20/00

CPC classification number: G06N3/04 ,  G06F3/0655 ,  G06F3/0656 ,  G06N3/063 ,  G06F3/061 ,  G06F3/0613 ,  G06F3/0635 ,  G06F3/0679 ,  G06F3/0688 ,  G06F5/16 ,  G06N3/02 ,  G06N3/06 ,  G06N20/00

Abstract: Examples herein describe hardware architecture for processing and accelerating data passing through layers of a neural network. In one embodiment, a reconfigurable integrated circuit (IC) for use with a neural network includes a digital processing engine (DPE) array, each DPE having a plurality of neural network units (NNUs). Each DPE generates different output data based on the currently processing layer of the neural network, with the NNUs parallel processing different input data sets. The reconfigurable IC also includes a plurality of ping-pong buffers designed to alternate storing and processing data for the layers of the neural network.