DISTRIBUTED STORAGE SPACE MANAGEMENT METHOD, COMPUTING DEVICE AND STORAGE MEDIUM

    公开(公告)号:US20240361959A1

    公开(公告)日:2024-10-31

    申请号:US18684941

    申请日:2023-01-11

    Inventor: Jun PIAO

    CPC classification number: G06F3/067 G06F3/0604 G06F3/0644 G06F3/0655

    Abstract: A distributed storage space management method, a computing device and a storage medium are provided. An embodiment is applied to a hardware smart card, which is deployed on a local host as a local hardware smart card. A corresponding storage space is partitioned for a local virtual device from a pre-configured storage device; the partitioned storage space is simulated to generate a simulated storage device corresponding to the local virtual device, for use by the local virtual device. A storage space application request of a remote hardware smart card is received, and according to the request, a corresponding storage space is partitioned for a remote virtual device from the pre-configured storage device, so that the partitioned storage space is simulated by means of the remote hardware smart card to generate a simulated storage device corresponding to the remote virtual device, for use by the remote virtual device.

    Electronic device, method, non-transitory computer-readable storage media, and UFS card including UFS storage device

    公开(公告)号:US12124730B2

    公开(公告)日:2024-10-22

    申请号:US17863401

    申请日:2022-07-13

    CPC classification number: G06F3/0655 G06F3/0604 G06F3/0679

    Abstract: An electronic device includes at least one processor, a Universal Flash Storage (UFS) device controller operatively coupled with the at least one processor, a UFS interface including a plurality of downstream lanes for transmitting data and a plurality of upstream lanes for transmitting data and storage including a cache memory and a plurality of non-volatile memories. The at least one processor transmits a first control signal to instruct measuring a temperature of the storage and identifying of the measured temperature exceeding a threshold value to the UFS device controller, receives a status signal indicating that the measured temperature exceeds the threshold value from the UFS device controller, and based on the status signal, transmits, to the UFS device controller, a second control signal to instruct that deactivating at least some of the plurality of downstream lanes and upstream lanes, or deactivating the cache memory in the storage.

    Controller to alter systems based on metrics and telemetry

    公开(公告)号:US12124729B2

    公开(公告)日:2024-10-22

    申请号:US17687018

    申请日:2022-03-04

    CPC classification number: G06F3/0655 G06F3/061 G06F3/0673

    Abstract: Systems, apparatuses, and methods related to a controller for managing metrics and telemetry are described. A controller includes a front end portion, a central controller portion, a back end portion, and a management unit. The central controller portion can include a cache to store data associated with the performance of the memory operations, metric logic configured to collect metrics related to performance of the memory operations, load telemetry logic configured to collect load telemetry associated with performance of the memory operations within a threshold time, and a storage area to store the collected metrics and the collected load telemetry. The management unit memory of the controller can store metrics and load telemetry associatAND ed with monitoring the characteristics of the memory controller, and based on the stored metrics and load telemetry, alter at least one characteristic of the computing system.

    SEMICONDUCTOR DEVICE FOR GENERATING AN INTERNAL VOLTAGE

    公开(公告)号:US20240345765A1

    公开(公告)日:2024-10-17

    申请号:US18351855

    申请日:2023-07-13

    Applicant: SK hynix Inc.

    CPC classification number: G06F3/0655 G06F3/0604 G06F3/0679 G11C11/4074

    Abstract: A semiconductor device includes an internal voltage control circuit including an amplifier circuit and a plurality of drivers. The internal voltage control circuit is configured to drive an internal voltage through the sharing of the amplifier circuit and a driver that is activated, among the plurality of drivers, after the start of a standby operation and an active operation. The semiconductor device also includes a core circuit including a plurality of banks. The core circuit is configured to perform an operation of a bank that is activated, among the plurality of banks, by receiving the internal voltage.

    METHODS AND SYSTEMS FOR HANDLING RACE CONDITIONS ASSOCIATED WITH A PRIMARY BIAS STATE IN A DISTRIBUTED STORAGE SYSTEM

    公开(公告)号:US20240338145A1

    公开(公告)日:2024-10-10

    申请号:US18296834

    申请日:2023-04-06

    Applicant: NetApp, Inc.

    CPC classification number: G06F3/0655 G06F3/0604 G06F3/067

    Abstract: According to an example, a computer-implemented method comprises initiating a first process for atomically setting the primary bias state with a first node of a primary storage cluster of a multi-site distributed storage system due to a temporary loss of connectivity to a mediator or a temporary mediator failure, releasing an atomic lock for the first process on the first node of the primary storage cluster, sending the first process and an associated first generation indicator to a first node of a secondary storage cluster of the multi-site distributed storage system to handle the first process for setting the primary bias state, and initiating a second process for atomically clearing a primary bias state with the first node or any node of the primary storage cluster based on detecting a connection to the mediator or detecting that the mediator is available.

    PERFORMANCE AND MEMORY ACCESS TRACKING
    10.
    发明公开

    公开(公告)号:US20240329833A1

    公开(公告)日:2024-10-03

    申请号:US18192694

    申请日:2023-03-30

    CPC classification number: G06F3/0604 G06F3/0655 G06F3/0673

    Abstract: Techniques for performing memory operations are disclosed herein. The techniques include generating a plurality of performance log entries based on observed operations; generating a plurality of memory access log entries based on the observed operations, wherein each performance log entry of the plurality of performance log entries are associated with one or more memory access log entries of the plurality of memory access log entries, wherein each performance log entry is associated with an epoch; and wherein each memory access log entry is associated with an epoch and a memory address range.

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