公开(公告)号：US12086521B2

公开(公告)日：2024-09-10

申请号：US17496198

申请日：2021-10-07

Applicant: Xilinx, Inc.

Inventor： Tharun Kumar Ksheerasagar ,  Rohit Bhadana ,  Hemant Kashyap ,  Pratyush Ranjan

IPC: G06F30/3312 ,  G06F30/327 ,  G06F119/12

CPC classification number: G06F30/3312 ,  G06F30/327 ,  G06F2119/12

Abstract: Circuit design simulation and clock event reduction may include detecting, using computer hardware, a plurality of models of a circuit design driven by a clock source by parsing the circuit design. The circuit design is a mixed language circuit design including a hardware description language (HDL) model and a high-level programming language (HLPL) model. Using the computer hardware, a clock requirement for the HLPL model for a simulation of the circuit design may be determined. The clock requirement of the HLPL model differs from a clock requirement of the HDL model. Using the computer hardware, an interface of the HLPL model may be modified based on the clock requirement of the HLPL model.

公开(公告)号：US20230114858A1

公开(公告)日：2023-04-13

申请号：US17496198

申请日：2021-10-07

Applicant: Xilinx, Inc.

Inventor： Tharun Kumar Ksheerasagar ,  Rohit Bhadana ,  Hemant Kashyap ,  Pratyush Ranjan

IPC: G06F30/3312 ,  G06F30/327

Abstract: Circuit design simulation and clock event reduction may include detecting, using computer hardware, a plurality of models of a circuit design driven by a clock source by parsing the circuit design. The circuit design is a mixed language circuit design including a hardware description language (HDL) model and a high-level programming language (HLPL) model. Using the computer hardware, a clock requirement for the HLPL model for a simulation of the circuit design may be determined. The clock requirement of the HLPL model differs from a clock requirement of the HDL model. Using the computer hardware, an interface of the HLPL model may be modified based on the clock requirement of the HLPL model.