公开(公告)号：US10379927B2

公开(公告)日：2019-08-13

申请号：US15340978

申请日：2016-11-01

Applicant: Xilinx, Inc.

Inventor： Lester S. Sanders ,  Shravanthi Katam ,  Abhinaya Katta ,  Jayaram Pvss

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/16 ,  G06F1/12 ,  G06F1/08 ,  G06F11/30

Abstract: An apparatus can include an interface circuit configured to receive an operating parameter and a control circuit coupled to the interface circuit and configured to store the operating parameter. The apparatus also can include a clock error detection circuit coupled to the control circuit. The clock error detection circuit can be configured to detect a clock error condition on a clock signal based upon the operating parameter and, responsive to detecting the clock error condition, generate a signal indicating an occurrence of the clock error condition.

公开(公告)号：US20180121280A1

公开(公告)日：2018-05-03

申请号：US15340978

申请日：2016-11-01

Applicant: Xilinx, Inc.

Inventor： Lester S. Sanders ,  Shravanthi Katam ,  Abhinaya Katta ,  Jayaram Pvss

IPC: G06F11/07 ,  G06F1/12

CPC classification number: G06F11/0757 ,  G06F1/08 ,  G06F1/12 ,  G06F11/0736 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/079 ,  G06F11/1604 ,  G06F11/3058

Abstract: An apparatus can include an interface circuit configured to receive an operating parameter and a control circuit coupled to the interface circuit and configured to store the operating parameter. The apparatus also can include a clock error detection circuit coupled to the control circuit. The clock error detection circuit can be configured to detect a clock error condition on a clock signal based upon the operating parameter and, responsive to detecting the clock error condition, generate a signal indicating an occurrence of the clock error condition.