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    DETECTING AND RECOVERING FROM TIMEOUTS IN SCALABLE MESH NETWORKS IN PROCESSOR-BASED DEVICES
    1.
    发明公开
    DETECTING AND RECOVERING FROM TIMEOUTS IN SCALABLE MESH NETWORKS IN PROCESSOR-BASED DEVICES 审中-公开

    公开(公告)号：US20240362103A1

    公开(公告)日：2024-10-31

    申请号：US18594858

    申请日：2024-03-04

    Applicant: QUALCOMM Incorporated

    Inventor： Gaurav Sanjeev Kirtane ,  Vinod Chamarty ,  Vignesh Deivaraj

    IPC: G06F11/07 ,  G06F11/30

    CPC classification number: G06F11/0772 ,  G06F11/0757 ,  G06F11/3027

    Abstract: Detecting and recovering from timeouts in scalable mesh circuits in processor-based devices is disclosed herein. In some exemplary aspects, a processor-based device provides an integrated circuit (IC) that includes an interconnect comprising a scalable mesh network communicatively coupled to a plurality of agents via a respective plurality of bridge devices. The plurality of agents includes a source agent and a target agent that communicate with a source bridge device and a target bridge device, respectively. The target bridge device receives a transaction directed to the target agent from the source agent via the interconnect. Upon receiving the transaction, the target bridge device initiates a timeout counter. If no response to the transaction received by the target bridge device from the target agent by the time the timeout counter expires, the target bridge device transmits to the source bridge device an indication that no response to the transaction was received.

    MANAGING DATA INTEGRITY USING A CHANGE IN A NUMBER OF DATA ERRORS AND AN AMOUNT OF TIME IN WHICH THE CHANGE OCCURRED
    4.
    发明公开
    MANAGING DATA INTEGRITY USING A CHANGE IN A NUMBER OF DATA ERRORS AND AN AMOUNT OF TIME IN WHICH THE CHANGE OCCURRED 审中-公开

    公开(公告)号：US20240345919A1

    公开(公告)日：2024-10-17

    申请号：US18755592

    申请日：2024-06-26

    Applicant: Micron Technology, Inc.

    Inventor： Ryan G. Fisher

    IPC: G06F11/10 ,  G06F11/07

    CPC classification number: G06F11/1048 ,  G06F11/0757 ,  G06F11/0793

    Abstract: Exemplary methods, apparatuses, and systems include performing an initial data integrity scan of a subset of memory at an initial time to determine an initial error rate for the subset of memory. The initial error rate and the initial time are stored. A subsequent integrity scan of the subset of memory is performed at a second time to determine a subsequent error rate for the subset of memory. A difference between the initial error rate and the subsequent error rate is determined. A difference between the initial time and the subsequent time is determined. A remedial action is selected using the difference between the initial error rate and the subsequent error rate and the difference between the initial time and the subsequent time and the remedial action is performed.

    Fault recovery system for functional circuits
    6.
    发明授权
    Fault recovery system for functional circuits 有权

    公开(公告)号：US12105583B2

    公开(公告)日：2024-10-01

    申请号：US17813737

    申请日：2022-07-20

    Applicant: NXP B.V.

    Inventor： Neha Srivastava ,  Hemant Nautiyal ,  Andres Barrilado Gonzalez

    IPC: G06F11/07 ,  G06F11/00

    CPC classification number: G06F11/0793 ,  G06F11/008 ,  G06F11/0706 ,  G06F11/0724 ,  G06F11/0757

    Abstract: A fault recovery system includes various fault management circuits that form a hierarchical structure. One fault management circuit detects a fault in a functional circuit and executes a recovery operation to recover the functional circuit from the fault. When the fault management circuit fails to recover the functional circuit from the fault within a predetermined time duration, a fault management circuit that is in a higher hierarchical level executes another recovery operation to recover the functional circuit from the fault. Such a fault management circuit is required to execute the corresponding recovery operation within another predetermined time duration to successfully recover the functional circuit from the fault. The fault recovery system thus implements the hierarchical structure of fault management circuits to recover the functional circuit from the fault.

    ERROR HANDLING FOR A MIXED MODE RFFE BUS
    8.
    发明公开
    ERROR HANDLING FOR A MIXED MODE RFFE BUS 审中-公开

    公开(公告)号：US20240311228A1

    公开(公告)日：2024-09-19

    申请号：US18183833

    申请日：2023-03-14

    Applicant: QUALCOMM Incorporated

    Inventor： Umesh SRIKANTIAH ,  Lalan Jee MISHRA ,  Richard Dominic WIETFELDT ,  Boris ALPIN ,  Francesco GATTA

    IPC: G06F11/07 ,  G06F13/42

    CPC classification number: G06F11/0793 ,  G06F11/0757 ,  G06F11/0772 ,  G06F13/4291

    Abstract: A receiving circuit has a clock generator circuit, a synchronization circuit and a controller. The clock generator circuit is configured to generate a base clock signal with a base frequency. The synchronization circuit is configured to synchronize edges in the base clock signal with edges in a Manchester-encoded data signal received over a serial bus. The controller is configured to detect that a first pulse received from the serial bus has a duration corresponding to a pulse duration defined for a first type of sequence start condition that indicates a first type of transaction during which the Manchester-encoded data signal is received over the serial bus; configure a first timer to expire after a first timeout period; and ignore the first pulse when signaling consistent with the first type of sequence start condition has not been received before the first timer expires.

    Watchdog timer device
    9.
    发明授权
    Watchdog timer device 有权

    公开(公告)号：US12093118B2

    公开(公告)日：2024-09-17

    申请号：US18191298

    申请日：2023-03-28

    Applicant: SANKEN ELECTRIC CO., LTD.

    Inventor： Naohiko Shimoyama

    IPC: G06F11/00 ,  G06F11/07

    CPC classification number: G06F11/0757 ,  G06F11/0721 ,  G06F11/0793

    Abstract: A watchdog timer device according to one or more embodiments may include a mode setting unit that sets a first mode or a second mode. In the first mode, the watchdog timer device monitors an operation state of a monitored device and generates an interrupt signal to cause the monitored device to perform recovery processing at a first timeout. In the second mode, the watchdog timer device monitors the recovery processing and generates a reset signal to restart the monitored device at a second timeout. The watchdog timer device uses different logic to execute determining the first timeout in the first mode and determining the second timeout in the second mode.

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