公开(公告)号：US20230153583A1

公开(公告)日：2023-05-18

申请号：US17454935

申请日：2021-11-15

Applicant: Xilinx, Inc.

Inventor： Ashish Sirasao ,  Vishal Kumar Jain ,  Sumit Nagpal

IPC: G06N3/04 ,  G06N3/10 ,  G06F8/41

CPC classification number: G06N3/049 ,  G06F8/41 ,  G06N3/10 ,  G06F16/9024

Abstract: Processing of a neural network specification includes gathering first layers of a neural network graph into groups of layers based on profiled compute times of the layers and equalized compute times between the groups. Each group is a subgraph of one or more of the layers of the neural network. The neural network graph is compiled into instructions for pipelined execution of the neural network graph by compute circuits. The compiling includes designating, for each first subgraph of the subgraphs having output activations that are input activations of a second subgraph of the subgraphs, operations of the first subgraph to be performed by a first compute circuit and operations of the second subgraph to be performed by a second compute circuit. The compute circuits are configured to execute the instructions.