公开(公告)号：US11003826B1

公开(公告)日：2021-05-11

申请号：US16397501

申请日：2019-04-29

Applicant: Xilinx, Inc.

Inventor： Srinivasan Dasasathyan ,  Padmini Gopalakrishnan ,  Vishal Tripathy ,  Vikas N. Vedamurthy ,  Sumit Nagpal

IPC: G06F30/392 ,  G06F30/327 ,  G06F111/04

Abstract: Strategies are stored in a memory arrangement, and each strategy includes a set of parameter settings for a design tool. The design tool identifies a set of features of an input circuit design and applies classification models to the input circuit design. Each classification model indicates one the strategies, and application of each classification model indicates a likelihood that use of the strategy would improve a metric of the input circuit design based on the set of features of the input circuit design. One strategy of the plurality of strategies is selected based on the likelihood that use of the one strategy would improve the metric of the input circuit design, and the design tool is configured with the set of parameter settings of the one strategy. The design tool then processes the input circuit design into implementation data that is suitable for making an integrated circuit (IC).

公开(公告)号：US20250086007A1

公开(公告)日：2025-03-13

申请号：US18464829

申请日：2023-09-11

Applicant: Xilinx, Inc.

Inventor： Sumit Nagpal ,  Abid Karumannil

IPC: G06F9/48 ,  G06F9/50

Abstract: Scheduling kernels on a system with heterogeneous compute circuits includes receiving, by a hardware processor, a plurality of kernels and a graph including a plurality of nodes corresponding to the plurality of kernels. The graph defines a control flow and a data flow for the plurality of kernels. The kernels are implemented within different ones of a plurality of compute circuits coupled to the hardware processor. A set of buffers for performing a job for the graph are allocated based, at least in part, on the data flow specified by the graph. Different ones of the kernels as implemented in the compute circuits are invoked based on the control flow defined by the graph.

公开(公告)号：US11561826B1

公开(公告)日：2023-01-24

申请号：US17096136

申请日：2020-11-12

Applicant: Xilinx, Inc.

Inventor： Sumit Nagpal ,  Abid Karumannil ,  Vishal Jain ,  Arun Kumar Patil

IPC: G06F9/46 ,  G06F9/48 ,  G06F16/901 ,  G06N3/08

Abstract: Scheduling work of a machine learning application includes instantiating kernel objects by a computer processor in response to input of kernel definitions. Each kernel object is of a kernel type indicating a compute circuit. The computer processor generates a graph in a memory. Each node represents a task and specifies an assignment of the task to one or more of the kernel objects, and each edge represents a data dependency. Task queues are created in the memory and assigned to queue tasks represented by the nodes. Kernel objects are assigned to the task queues, and the tasks are enqueued by threads executing the kernel objects, based on assignments of the kernel objects to the task queues and assignments of the tasks to the kernel objects. Tasks are dequeued by the threads, and the compute circuits are activated to initiate processing of the dequeued tasks.

公开(公告)号：US10067642B1

公开(公告)日：2018-09-04

申请号：US14639768

申请日：2015-03-05

Applicant: Xilinx, Inc.

Inventor： David Robinson ,  Sumit Nagpal ,  Prashanth Kumar ,  Shreegopal S. Agrawal

IPC: G06F17/30 ,  G06F3/0482 ,  G06F9/38

Abstract: Core processing and parameterization may include detecting, using a processor, a super parameter within a core, and, responsive to the detecting, automatically creating, using the processor, a data structure within a memory element having a hierarchy and having a parameter of the core. The data structure may be set as a value of the super parameter of the core.

公开(公告)号：US09183337B1

公开(公告)日：2015-11-10

申请号：US14455029

申请日：2014-08-08

Applicant: Xilinx, Inc.

Inventor： Sumit Nagpal ,  Sreevidya Maguluri ,  Prashanth Kumar

IPC: G06F17/50

CPC classification number: G06F17/505

Abstract: A method of processing a circuit design in a circuit design tool includes: identifying selection of a parameterized core to be instantiated in a description of the circuit design managed by the circuit design tool and configured for implementation in target hardware; processing a configuration file for the parameterized core to select a set of parameter values from a plurality of sets of parameter values dynamically based at least in part on the target hardware; creating an instance of the parameterized core in the circuit design having the selected set of parameter values; and implementing the circuit design for the target hardware.

Abstract translation: 一种在电路设计工具中处理电路设计的方法包括：识别在由电路设计工具管理的电路设计的描述中要实例化的参数化核的选择，并配置为在目标硬件中实现; 处理参数化核心的配置文件以至少部分地基于目标硬件动态地从多个参数值集合中选择一组参数值; 在具有所选择的参数值集合的电路设计中创建参数化核心的实例; 并实现目标硬件的电路设计。

公开(公告)号：US08769477B1

公开(公告)日：2014-07-01

申请号：US13756339

申请日：2013-01-31

Applicant: Xilinx, Inc.

Inventor： Yogesh Gathoo ,  Siddharth Rele ,  Gregory A. Brown ,  Avdhesh Palliwal ,  Gangadhar Budde ,  Sumit Nagpal

IPC: G06F17/50

CPC classification number: G06F17/5054

Abstract: A user interface for a computer-aided design tool includes a display. The display includes a visualization of a processor system of a system-on-a-chip (SOC). The visualization includes a plurality of blocks and each block represents a component of the processor system. Each block visually indicates a configuration status of the component represented by the block.

Abstract translation: 用于计算机辅助设计工具的用户界面包括显示器。 显示器包括片上系统（SOC）的处理器系统的可视化。 可视化包括多个块，并且每个块表示处理器系统的组件。 每个块可视地指示由块表示的组件的配置状态。

公开(公告)号：US20240211675A1

公开(公告)日：2024-06-27

申请号：US18145704

申请日：2022-12-22

Applicant: Xilinx, Inc.

Inventor： Mohammed Bader Alam ,  Goutham Pocklassery ,  Ravishankar Menon ,  Sumit Nagpal ,  Mahesh Suresh Mahadurkar ,  Padmini Gopalakrishnan

IPC: G06F30/394 ,  G06F30/392

CPC classification number: G06F30/394 ,  G06F30/392

Abstract: A design for a programmable integrated circuit (IC) is synthesized and includes an inference engine and a data transformer. A portion of the design including the data transformer is designated as a dynamic function exchange (DFX) module. The inference engine is excluded from the DFX module. The design is implemented, by placing and routing, such that the DFX module is confined to a defined physical area of the programmable integrated circuit. An abstract shell for the design specifying boundary connections of the DFX module as placed and routed is generated. A locked version of the design as placed and routed with the DFX module removed is generated. The method includes implementing a different data transformer as a further DFX module for the design using the abstract shell.

公开(公告)号：US20230153583A1

公开(公告)日：2023-05-18

申请号：US17454935

申请日：2021-11-15

Applicant: Xilinx, Inc.

Inventor： Ashish Sirasao ,  Vishal Kumar Jain ,  Sumit Nagpal

IPC: G06N3/04 ,  G06N3/10 ,  G06F8/41

CPC classification number: G06N3/049 ,  G06F8/41 ,  G06N3/10 ,  G06F16/9024

Abstract: Processing of a neural network specification includes gathering first layers of a neural network graph into groups of layers based on profiled compute times of the layers and equalized compute times between the groups. Each group is a subgraph of one or more of the layers of the neural network. The neural network graph is compiled into instructions for pipelined execution of the neural network graph by compute circuits. The compiling includes designating, for each first subgraph of the subgraphs having output activations that are input activations of a second subgraph of the subgraphs, operations of the first subgraph to be performed by a first compute circuit and operations of the second subgraph to be performed by a second compute circuit. The compute circuits are configured to execute the instructions.

公开(公告)号：US09710582B1

公开(公告)日：2017-07-18

申请号：US14974217

申请日：2015-12-18

Applicant: Xilinx, Inc.

Inventor： Sumit Nagpal ,  Siddharth Rele ,  Avdhesh Palliwal

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F2217/66 ,  G06F2217/68

Abstract: Implementing a circuit design may include, responsive to a user input selecting a design, executing an implementation script of the design using the processor. Executing the implementation script may generate instructions for generating a circuit design from the design. Responsive to the instructions and using the processor, cores of the design may be automatically instantiated and connected.

公开(公告)号：US08938704B1

公开(公告)日：2015-01-20

申请号：US14444693

申请日：2014-07-28

Applicant: Xilinx, Inc.

Inventor： Siddharth Rele ,  David A. Knol ,  Sumit Nagpal ,  Avdhesh Palliwal ,  Brendan M. O'Higgins

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F17/5081

Abstract: An exemplary method of implementing a circuit design for a programmable integrated circuit (IC) includes, on at least one programmed processor, performing operations including: generating a description of circuit components of the circuit design including first portion of a circuit module that is independent of assignment of resources of the programmable IC; assigning a plurality of the resources of the programmable IC to a plurality of the circuit components including determining at least one resource assignment for the circuit module; and generating a physical implementation of the circuit components for implementation in the programmable IC, including generating a second portion of the circuit module that is dependent on the at least one resource assignment, and combining the second portion of the circuit module with the first portion of the circuit module.

Abstract translation: 实现可编程集成电路（IC）的电路设计的示例性方法包括在至少一个编程的处理器上执行操作，包括：产生电路设计的电路部件的描述，该电路设计包括电路模块的独立于 可编程IC资源的分配; 将多个可编程IC的资源分配给多个电路组件，包括确定电路模块的至少一个资源分配; 以及生成用于在可编程IC中实现的电路部件的物理实现，包括生成依赖于至少一个资源分配的电路模块的第二部分，以及将电路模块的第二部分与 电路模块。