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    Differential amplification circuit
    1.
    发明授权
    Differential amplification circuit 失效
    差分放大电路

    公开(公告)号：US4264873A

    公开(公告)日：1981-04-28

    申请号：US56422

    申请日：1979-07-10

    申请人： Yasuo Kominami ,  Masahiro Yamamura ,  Katsuji Mizumoto ,  Toshihide Hanada

    发明人： Yasuo Kominami ,  Masahiro Yamamura ,  Katsuji Mizumoto ,  Toshihide Hanada

    IPC分类号： H03F1/30 ,  H03F3/45 ,  H03F3/04

    CPC分类号： H03F3/45085 ,  H03F3/45 ,  H03F2203/45388 ,  H03F2203/45462 ,  H03F2203/45496 ,  H03F2203/45508 ,  H03F2203/45611 ,  H03F2203/45612 ,  H03F2203/45652 ,  H03F2203/45656

    摘要： A differential amplification is disclosed which comprises differential paired transistors. The direct bias current flowing in the differential paired transistors is determined by a constant current flowing from a first constant current circuit connected to the emitters of the differential paired transistors. The collector current of one of the differential paired transistors is caused to flow as an input current in a high-precision current mirror circuit. The current value of the constant current flowing in the first constant current circuit is set at 2Io. Since a direct base current Ib flows in the differential paired transistors, the current value of the collector current of one of the differential paired transistors is (Io-Ib). Accordingly, the high-precision current mirror circuit generates an output current of a current value of (Io-Ib) at the output terminal thereof. The differential amplification circuit includes a second constant current circuit having a current value Io corresponding to 1/2 of the current value of the constant current flowing in the first constant current circuit. A bias transistor is connected between the high-precision current mirror circuit and the second constant current circuit, and the direct base current Ib flows in this bias transistor. Accordingly, in the equilibrium state between the differential paired transistors, the output current appearing at the output terminal of the high precision current mirror circuit becomes zero, and the offset output current can be eliminated or moderated.

    摘要翻译： 公开了包括差分成对晶体管的差分放大器。 在差分成对晶体管中流动的直流偏置电流由连接到差分成对晶体管的发射极的第一恒定电流电流的恒定电流确定。 导致差分成对晶体管之一的集电极电流作为高精度电流镜电路中的输入电流流动。 在第一恒流电路中流动的恒定电流的电流值设定为2Io。 由于直流基极电流Ib流入差分成对晶体管，因此差分成对晶体管之一的集电极电流的电流值为（Io-Ib）。 因此，高精度电流镜电路在其输出端产生电流值（Io-Ib）的输出电流。 差分放大电路包括具有对应于在第一恒流电路中流动的恒定电流的电流值的1/2的电流值I 1的第二恒流电路。 偏置晶体管连接在高精度电流镜电路和第二恒流电路之间，直流基极电流Ib流入该偏置晶体管。 因此，在差分成对晶体管之间的平衡状态下，出现在高精度电流镜电路的输出端的输出电流变为零，并且可以消除或缓和偏移输出电流。

    Constant voltage output circuit
    2.
    发明授权
    Constant voltage output circuit 失效
    恒压输出电路

    公开(公告)号：US4283674A

    公开(公告)日：1981-08-11

    申请号：US59030

    申请日：1979-07-19

    申请人： Yasuo Kominami ,  Masahiro Yamamura ,  Katsuji Mizumoto ,  Toshihide Hanada

    发明人： Yasuo Kominami ,  Masahiro Yamamura ,  Katsuji Mizumoto ,  Toshihide Hanada

    IPC分类号： G05F1/56 ,  G05F3/18 ,  G05F3/22

    CPC分类号： G05F3/18

    摘要： This invention relates to a constant voltage output circuit using, as its reference potential source, power source feed terminals for feeding a power source voltage to a reference potential source of a given circuit. The constant voltage output circuit includes a series circuit of an npn transistor and a pnp transistor interposed between the reference potential source of the given circuit and the power source feed terminals, means for biasing the base potential of the pnp transistor by a predetermined potential with respect to the potential of the power source feed terminals, and an emitter follower circuit disposed in the collector output circuit of the npn transistor of the series circuit, and forming a negative feed-back circuit.

    摘要翻译： 本发明涉及使用作为其参考电位源的用于将电源电压馈送到给定电路的参考电位源的电源馈电端子的恒压输出电路。 恒压输出电路包括插入在给定电路的参考电位源和电源馈电端子之间的npn晶体管和pnp晶体管的串联电路，用于将pnp晶体管的基极电位偏置预定电位的装置 电源馈电端子的电位和设置在串联电路的npn晶体管的集电极输出电路中的射极跟随器电路，并形成负反馈电路。