Method and system for auto parallelization of zero-trip loops through induction variable substitution

    公开(公告)号:US20060048119A1

    公开(公告)日:2006-03-02

    申请号:US10926594

    申请日:2004-08-26

    IPC分类号: G06F9/45

    CPC分类号: G06F8/443 G06F8/452

    摘要: A method and system of auto parallelization of zero-trip loops that substitutes a nested basic linear induction variable by exploiting a parallelizing compiler is provided. Provided is a use of a max{0,N} variable for loop iterations in case of no information is known about the value of N, for a typical loop iterating from 1 to N, in which N is the loop invariant. For the nested basic induction variables, an induction variable substitution process is applied to the nested loops starting from the innermost loop to the outermost one. Then a removal of the max operator afterwards through a copy propagation pass of the IBM compiler is provided. In doing so, the loop dependency on the induction variable is eliminated and an opportunity for a parallelizing compiler to parallel the outermost loop is provided.

    Method and System for Auto Parallelization of Zero-Trip Loops Through the Induction Variable Substitution
    2.
    发明申请
    Method and System for Auto Parallelization of Zero-Trip Loops Through the Induction Variable Substitution 失效
    通过感应变量替代自动并联零行程循环的方法和系统

    公开(公告)号:US20090158018A1

    公开(公告)日:2009-06-18

    申请号:US12356978

    申请日:2009-01-21

    IPC分类号: G06F9/44

    CPC分类号: G06F8/443 G06F8/452

    摘要: A method and system of auto parallelization of zero-trip loops that substitutes a nested basic linear induction variable by exploiting a parallelizing compiler is provided. Provided is a use of a max{0,N} variable for loop iterations in case of no information is known about the value of N, for a typical loop iterating from 1 to N, in which N is the loop invariant. For the nested basic induction variables, an induction variable substitution process is applied to the nested loops starting from the innermost loop to the outermost one. Then a removal of the max operator afterwards through a copy propagation pass of the IBM compiler is provided. In doing so, the loop dependency on the induction variable is eliminated and an opportunity for a parallelizing compiler to parallel the outermost loop is provided.

    摘要翻译: 提供了通过利用并行化编译器代替嵌套的基本线性感应变量的零跳行循环自动并行化的方法和系统。 提供了对于从1到N迭代的典型循环,在没有关于N的值的信息的情况下,使用max {0,N}变量进行循环迭代,其中N是循环不变量。 对于嵌套的基本感应变量,将诱导变量替换过程应用于从最内循环到最外层循环的嵌套循环。 然后,通过IBM编译器的复制传播传递,随后删除最大运算符。 在这样做时,消除了对感应变量的循环依赖性,并且提供并行化编译器并行最外层循环的机会。

    Auto parallelization of zero-trip loops through the induction variable substitution
    3.
    发明授权
    Auto parallelization of zero-trip loops through the induction variable substitution 失效
    通过感应变量替代自动并联零跳闸回路

    公开(公告)号:US08375375B2

    公开(公告)日:2013-02-12

    申请号:US12356978

    申请日:2009-01-21

    IPC分类号: G06F9/45

    CPC分类号: G06F8/443 G06F8/452

    摘要: A method and system of auto parallelization of zero-trip loops that substitutes a nested basic linear induction variable by exploiting a parallelizing compiler is provided. Provided is a use of a max{0,N} variable for loop iterations in case of no information is known about the value of N, for a typical loop iterating from 1 to N, in which N is the loop invariant. For the nested basic induction variables, an induction variable substitution process is applied to the nested loops starting from the innermost loop to the outermost one. Then a removal of the max operator afterwards through a copy propagation pass of the IBM compiler is provided. In doing so, the loop dependency on the induction variable is eliminated and an opportunity for a parallelizing compiler to parallel the outermost loop is provided.

    摘要翻译: 提供了通过利用并行化编译器代替嵌套的基本线性感应变量的零跳行循环自动并行化的方法和系统。 提供了对于从1到N迭代的典型循环,在没有关于N的值的信息的情况下,使用max {0,N}变量进行循环迭代,其中N是循环不变量。 对于嵌套的基本感应变量,将诱导变量替换过程应用于从最内循环到最外层循环的嵌套循环。 然后,通过IBM编译器的复制传播传递,随后删除最大运算符。 在这样做时,消除了对感应变量的循环依赖性,并且提供并行化编译器并行最外层循环的机会。

    Method and system for auto parallelization of zero-trip loops through induction variable substitution
    4.
    发明授权
    Method and system for auto parallelization of zero-trip loops through induction variable substitution 失效
    通过感应变量替代自动并联零跳闸回路的方法和系统

    公开(公告)号:US07487497B2

    公开(公告)日:2009-02-03

    申请号:US10926594

    申请日:2004-08-26

    IPC分类号: G06F9/45

    CPC分类号: G06F8/443 G06F8/452

    摘要: A method and system of auto parallelization of zero-trip loops that substitutes a nested basic linear induction variable by exploiting a parallelizing compiler is provided. Provided is a use of a max{0,N} variable for loop iterations in case of no information is known about the value of N, for a typical loop iterating from 1 to N, in which N is the loop invariant. For the nested basic induction variables, an induction variable substitution process is applied to the nested loops starting from the innermost loop to the outermost one. Then a removal of the max operator afterwards through a copy propagation pass of the IBM compiler is provided. In doing so, the loop dependency on the induction variable is eliminated and an opportunity for a parallelizing compiler to parallel the outermost loop is provided.

    摘要翻译: 提供了通过利用并行化编译器代替嵌套的基本线性感应变量的零跳行循环自动并行化的方法和系统。 提供了对于从1到N迭代的典型循环,在没有关于N的值的信息的情况下,使用max {0,N}变量进行循环迭代,其中N是循环不变量。 对于嵌套的基本感应变量,将诱导变量替换过程应用于从最内循环到最外层循环的嵌套循环。 然后,通过IBM编译器的复制传播传递,随后删除最大运算符。 在这样做时,消除了对感应变量的循环依赖性,并且提供并行化编译器并行最外层循环的机会。

    Framework for parallelizing general reduction
    5.
    发明授权
    Framework for parallelizing general reduction 失效
    平行一般裁减的框架

    公开(公告)号:US08037462B2

    公开(公告)日:2011-10-11

    申请号:US11461863

    申请日:2006-08-02

    IPC分类号: G06F9/45

    CPC分类号: G06F8/452

    摘要: A method for providing parallel processing capabilities including: performing scalar and array privatization analysis via a compiler; checking whether an assignment statement is reducible; recognizing reduction patterns through a pattern matching algorithm; classifying a reduction type of each of the reduction patterns; and performing transformations and code generation for each reduction the reduction type of each of the reduction patterns.

    摘要翻译: 一种提供并行处理能力的方法,包括:通过编译器进行标量和阵列私有化分析; 检查一个赋值语句是否可以减少; 通过模式匹配算法识别缩减模式; 对每种减少模式的减少类型进行分类; 并且对每个减少模式的每个还原类型进行每个缩减执行变换和代码生成。

    FRAMEWORK FOR PARALLELIZING GENERAL REDUCTION
    6.
    发明申请
    FRAMEWORK FOR PARALLELIZING GENERAL REDUCTION 失效
    平行一般减少的框架

    公开(公告)号:US20080052689A1

    公开(公告)日:2008-02-28

    申请号:US11461863

    申请日:2006-08-02

    IPC分类号: G06F9/45 G06F9/44

    CPC分类号: G06F8/452

    摘要: A method for providing parallel processing capabilities including: performing scalar and array privatization analysis via a compiler; checking whether an assignment statement is reducible; recognizing reduction patterns through a pattern matching algorithm; classifying a reduction type of each of the reduction patterns; and performing transformations and code generation for each reduction the reduction type of each of the reduction patterns.

    摘要翻译: 一种提供并行处理能力的方法,包括:通过编译器进行标量和阵列私有化分析; 检查一个赋值语句是否可以减少; 通过模式匹配算法识别缩减模式; 对每种减少模式的减少类型进行分类; 并且对每个减少模式的每个还原类型进行每个缩减执行变换和代码生成。