公开(公告)号：US06812158B1

公开(公告)日：2004-11-02

申请号：US10335177

申请日：2002-12-31

Applicant: Wen-Chin Yeh ,  Venkatesh Gopinath ,  Arvind Kamath

Inventor： Wen-Chin Yeh ,  Venkatesh Gopinath ,  Arvind Kamath

IPC: H01L2131

CPC classification number: H01L21/02238 ,  H01L21/02255 ,  H01L21/02299 ,  H01L21/31658 ,  H01L21/823462 ,  H01L21/823481 ,  Y10S438/981

Abstract: Growth of multiple gate oxides. By implanting different sites of a wafer with different doses of an oxide growth retardant, the entire wafer can grow oxides of different thicknesses even after being exposed to the same oxidation environment. The process is modular insofar as the implantation of one site has no effect on rate of growth of other sites.

Abstract translation: 多栅极氧化物的生长。 通过用不同剂量的氧化物生长阻滞剂植入晶片的不同位置，即使在暴露于相同的氧化环境之后，整个晶片也可以生长不同厚度的氧化物。 该过程是模块化的，因为一个位点的植入对其他位点的生长速率没有影响。

公开(公告)号：US06544829B1

公开(公告)日：2003-04-08

申请号：US10251016

申请日：2002-09-20

Applicant: Venkatesh Gopinath ,  Mohammad Mirabedini ,  Charles E. May ,  Arvind Kamath

Inventor： Venkatesh Gopinath ,  Mohammad Mirabedini ,  Charles E. May ,  Arvind Kamath

IPC: H01L218238

CPC classification number: H01L21/823835 ,  H01L21/823814 ,  H01L21/823878

Abstract: A method of fabricating a substantially completely silicided polysilicon gate electrode in a CMOS process flow. A hard mask material is formed on an integrated circuit substrate, where the integrated circuit substrate includes an unpatterned polysilicon layer that overlies a gate oxide layer, and a well region disposed between isolation structures. Portions of the hard mask material are removed to define gate electrode masks that overlie first portions of the unpatterned polysilicon layer and the gate oxide layer, leaving exposed second portions of the unpatterned polysilicon layer and the gate oxide layer. The integrated circuit substrate is exposed to a dopant that passes through the second portions of the gate oxide layer but does not penetrate the first portions of the gate oxide layer that underlie the gate electrode masks, which defines source drain regions in the well region. The exposed second portions of the unpatterned polysilicon layer are removed to define polysilicon gate electrode precursors under the gate electrode masks. The gate electrode masks are removed from the polysilicon gate electrode precursors, and a metal layer is deposited over the polysilicon gate electrode precursors and the source drain regions. The integrated circuit substrate is annealed to substantially completely consume the polysilicon gate electrode precursors and form silicide gate electrodes from the polysilicon gate electrode precursors and the overlying metal layer, by which silicide contacts in the source drain regions are also formed.

Abstract translation: 一种在CMOS工艺流程中制造基本上完全硅化的多晶硅栅电极的方法。 在集成电路基板上形成硬掩模材料，其中集成电路基板包括覆盖在栅极氧化物层上的未图案化的多晶硅层和设置在隔离结构之间的阱区域。 去除硬掩模材料的部分以限定覆盖未图案化多晶硅层和栅极氧化物层的第一部分的栅电极掩模，留下未图案化的多晶硅层和栅极氧化物层的暴露的第二部分。 集成电路基板暴露于穿过栅极氧化物层的第二部分但不穿过限定阱区中的源极漏极区域的栅极电极掩模之下的栅极氧化物层的第一部分的掺杂剂。 去除未图案化的多晶硅层的暴露的第二部分以在栅极电极掩模下限定多晶硅栅电极前体。 栅极电极掩模从多晶硅栅电极前驱体去除，并且金属层沉积在多晶硅栅极电极前体和源极漏极区上。 将集成电路基板退火以基本上完​​全消耗多晶硅栅极电极前体，并从多晶硅栅极电极前体和上覆金属层形成硅化物栅极电极，由此源极漏极区域中的硅化物接触也形成。