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公开(公告)号：US10984695B2
公开(公告)日：2021-04-20
申请号：US16543125
申请日：2019-08-16
Inventor： Yulong Xiong , Liugang Zhou , Tao Li , Yizhan Han , Jianwei Sun , Liu He
IPC: G09G3/20
Abstract: A display driving device is disclosed. The display driving device includes: a data signal end for providing a data signal, a source line, and a switching circuit. The source line can transmit the data signal to a first pixel circuit and a second pixel circuit. Along a direction of the source line, a distance between the second pixel circuit and the data signal end is larger than a distance between the first pixel circuit and the data signal end. The switching circuit is between the data signal end and the source line, and can be turned on in response to a first control signal, and can be turned on in response to a second control signal. A turned-on time period of the switching circuit in response to the second control signal is longer than a turned-on time period of the switching circuit in response to the first control signal.
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公开(公告)号：US20210104700A1
公开(公告)日：2021-04-08
申请号：US16465951
申请日：2018-10-29
Inventor： Jie Chen , Jiewei Li , Mengyu Luan
Abstract: A display panel, a method for manufacturing the same, and a display device are provided. The display panel includes a first substrate and a second substrate opposite to each other; a display structure on a side of the first substrate facing the second substrate; a sealant surrounding the display structure; and a barrier structure surrounding the display structure and located between the display structure and the sealant, the barrier structure being disposed on one of the first substrate or the second substrate and being spaced apart from the other of the first substrate or the second substrate.
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公开(公告)号：US20210097950A1
公开(公告)日：2021-04-01
申请号：US16994891
申请日：2020-08-17
Inventor： Ke Dai , Yunyun Liang , Liugang Zhou , Zhenlin Qu , Liu He , Qing Li , Jun Wang , Yu Quan , Xiaofeng Yin , Liwei Zhou , Lin Zhang , Tao Li , Yulong Xiong
Abstract: The present disclosure provides a driving circuit and driving method for a liquid crystal display panel, and a display device. The driving circuit includes: a signal collector, configured to collect a backlight control signal; and a timing control chip, configured to determine whether a BLU is in the bright state time period or in the dark state time period, and retrieve a first gate control signal from a memory chip and output the first gate control signal to a gate driving circuit, when determining that the BLU is in the bright state time period, or retrieve a second gate control signal from the memory chip and output the second gate control signal to the gate driving circuit, when determining that the BLU is in the dark state time period.
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94.发明申请公开(公告)号：US20210063831A1
公开(公告)日：2021-03-04
申请号：US16832155
申请日：2020-03-27
Inventor： Yuntian ZHANG , Peng JIANG , Ke DAI , Jingang LIU , Lihui HAN , Zhonghou WU , Chunxu ZHANG , Mengmeng LI
IPC: G02F1/1362 , G09G3/34 , G02F1/1368 , G02F1/1333 , G02F1/13357
Abstract: An array substrate includes a substrate, at least one first light-shielding layer disposed above the substrate, semiconductor retention layers disposed on a side of the at least one first light-shielding layer facing away from the substrate, and data lines disposed on a side of the plurality of semiconductor retention layers facing away from the at least one first light-shielding layer. One first light-shielding layer of the at least one first light-shielding layer is disposed between one semiconductor retention layer of the semiconductor retention layers and the substrate, and an orthographic projection of the first light-shielding layer on the substrate covers an orthographic projection of the semiconductor retention layer on the substrate. The data lines are in one-to-one correspondence with the semiconductor retention layers, and an orthographic projection of each data line on the substrate overlaps with an orthographic projection of a corresponding semiconductor retention layer on the substrate.
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公开(公告)号：US20210049969A1
公开(公告)日：2021-02-18
申请号：US16994217
申请日：2020-08-14
Inventor： Jun WANG , Liugang ZHOU , Jingang LIU , Ke DAI , Xiaofeng YIN , Jianwei SUN , Liu HE , Zhenlin QU , Qing LI , Yunyun LIANG , Yulong XIONG , Yu QUAN
Abstract: A display driving method includes: determining, by a timing controller, an actual grayscale value of a sub-pixel image in an X-th row and a Y-th column according to a preset grayscale value of a sub-pixel image in an (X−1)-th row and the Y-th column and a preset grayscale value of the sub-pixel image in the X-th row and the Y-th column of an image frame to be displayed. The image frame to be displayed includes J rows and Q columns of sub-pixel images. X is greater than or equal to 2, and is less than or equal to J. Y is greater than or equal to 1, and is less than or equal to Q, and X, Y, J, and Q are all integers.
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Patent Agency Ranking
公开(公告)号：US10902803B2
公开(公告)日：2021-01-26
申请号：US16479764
申请日：2018-11-23
Inventor： Yizhan Han , Shou Li , Liugang Zhou , Tao Li , Yulong Xiong , Jianwei Sun
IPC: G09G3/36
Abstract: The disclosure discloses a display panel, a voltage adjustment method thereof, and a display device, and the display panel includes: at least two reference sub-pixels; a voltage compensation element coupled respectively with respective reference sub-pixels; and a power management element coupled with the voltage compensation element, wherein the voltage compensation element is configured to acquire valid values of pixel voltage of the respective reference sub-pixels when the at least two reference sub-pixels receive the same data voltage, and to generate a compensation signal of gate off voltage for the purpose of making the acquired valid values of the pixel voltage of the respective reference sub-pixels uniform; and the power management element is configured to adjust a voltage value of the gate off voltage according to the compensation signal of the gate off voltage.
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97.发明授权公开(公告)号：US10818261B2
公开(公告)日：2020-10-27
申请号：US16460245
申请日：2019-07-02
Inventor： Bin Luo , Hao Chen , Jincheng Jia , Yunfei Liu , Wei Zhang
IPC: G09G3/36
Abstract: A gate driving unit circuit pair and a driving method thereof, a gate driving circuit and a display device are provided. The gate driving unit circuit pair includes two gate driving unit circuits, each of which includes a first output sub-circuit, a second output sub-circuit, and a coupling and isolation sub-circuit. The coupling and isolation sub-circuit is configured to: if the first output sub-circuit outputs signal, isolate the signal of the first output terminal from the signal of the second output terminal; or else, couple the signal of the first output terminal to the second output terminal.
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98.发明申请公开(公告)号：US20200256667A1
公开(公告)日：2020-08-13
申请号：US16651973
申请日：2019-08-22
Inventor： Yuntian ZHANG , Chunxu ZHANG , Zhonghou WU , Qiong ZHANG , Ke DAI , Haipeng YANG , Peng JIANG
IPC: G01B11/16
Abstract: An optical apparatus includes a coherent light source; a transmission assembly configured to receive light emitted by the coherent light source, split the light into object light and reference light so that the object light and the reference light travel along different paths receive object light reflected by an object to be measured, and combine the object light reflected by the object to be measured and the reference light; and a photosensitive camera disposed at an output of the transmission assembly, and configured to receive combined light and process the combined light to record light intensity information capable of characterizing a spatial position of a surface of the object to be measured.
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99.发明申请公开(公告)号：US20200243150A1
公开(公告)日：2020-07-30
申请号：US16551945
申请日：2019-08-27
Inventor： Mo CHEN , Kai CHEN , Fei HAN , Fangqing LI , Wangdi WU
Abstract: A shift register including an input circuit, an output circuit, a first output control circuit, a second output control circuit, a reset circuit, a first reset control circuit, a second reset control circuit, and an energy-storing circuit. The first output control circuit is configured to transfer a clock signal present at a third clock signal terminal to a first node in response to the clock signal at the third clock signal terminal being active. The second output control circuit is configured to transfer a voltage present at a first voltage terminal to the first node in response to a clock signal at a fourth clock signal terminal being active.
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公开(公告)号：US20200243039A1
公开(公告)日：2020-07-30
申请号：US16668211
申请日：2019-10-30
Inventor： Yizhan HAN , Ke DAI , Liugang ZHOU
IPC: G09G5/00
Abstract: A chip-on-film and a display device. The chip-on-film includes a substrate, at least one chip on the substrate, input terminals on the substrate, and output terminals on the substrate. The input terminals are configured to receive printed-circuit-board signals. The output terminals include data signal output sub-terminals configured to output display panel data signals. The output terminals lack an output sub-terminal configured to output a display panel scanning signal.
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