公开(公告)号：US06617690B1

公开(公告)日：2003-09-09

申请号：US10218292

申请日：2002-08-14

申请人： Stephen M. Gates ,  Timothy J. Dalton ,  John A. Fitzsimmons

发明人： Stephen M. Gates ,  Timothy J. Dalton ,  John A. Fitzsimmons

IPC分类号： H01L2940

CPC分类号： H01L23/53295 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： Novel interconnect structures possessing a relatively low internal stress and dielectric constant for use in semiconductor devices are provided herein. The novel interconnect structures comprise a first layer having a coefficient of thermal expansion greater than about 20 ppm and a first internal stress associated therewith, the first layer having a first set of metallic lines formed therein; a second layer having a coefficient of thermal expansion less than about 20 ppm and a second internal stress associated therewith, the second layer having a second set of metallic lines formed therein; and one or more stress adjustment cap layers formed between the first layer and the second layer, the cap layer(s) having a third internal stress to offset the first stress of the first layer and the second stress of the second layer and inducing a favorable relief of stress on the interconnect structure. Methods for making a semiconductor device having a substantially reduced internal stress are also provided.

摘要翻译： 本文提供了具有用于半导体器件的相对低的内应力和介电常数的新型互连结构。 新颖的互连结构包括具有大于约20ppm的热膨胀系数的第一层和与其相关联的第一内部应力，第一层具有形成在其中的第一组金属线; 具有小于约20ppm的热膨胀系数的第二层和与其相关联的第二内应力，所述第二层在其中形成有第二组金属线; 以及形成在所述第一层和所述第二层之间的一个或多个应力调整盖层，所述盖层具有第三内应力以抵消所述第一层的第一应力和所述第二层的所述第二应力，并诱导有利的 减轻互连结构上的应力。 还提供了制造具有显着降低的内部应力的半导体器件的方法。