Abstract:
A traffic management processor for scheduling packets for transmission across a network includes a departure time calculator for generating a departure time for each packet, a departure time prioritizer for comparing the departure times with each other to determine which of the departure times is the earliest, and a token generator for generating a token for each packet.
Abstract:
A low power content addressable memory (CAM) device. The CAM device receives an N-bit comparand value and, in response, activates less than N compare lines within the CAM device to compare each of the N bits of the comparand value with contents of CAM cells coupled to the N compare lines.
Abstract:
A traffic management processor for managing a number of traffic flows each including one or more packets includes a content address memory (CAM) device having a plurality of rows, each row storing a flow identification (ID) for a corresponding packet, the flow ID indicating to which traffic flow the packet belongs, a departure time table for storing departure times for the packets, and compare logic for comparing the departure times with each other to determine which departure time is the earliest.
Abstract:
A digital signal processor having priority logic coupled to an array of storage elements, the priority logic to provide to a priority signal lines an indication of a location of a particular number in the array of storage elements. The priority logic includes compare circuits where each compare circuit is coupled to one of the storage elements in the array of storage elements. Each compare circuit has a first input coupled to a storage element, a second input coupled to a match line, and an input/output line coupled to one of the priority signal lines. The priority logic also includes a delay circuit coupled to each of the compare circuits.
Abstract:
A content addressable memory (CAM) device including a CAM array, encoding circuit, address circuit and error checking circuit. The encoding circuit generates an address value that corresponds to one of a plurality of match lines included within the CAM array. The address circuit receives the address value from the encoding circuit and enables a data word to be output from a CAM array storage location indicated by the address value. The error checking circuit receives the data word output from the storage location and determines whether the data word contains an error.
Abstract:
A method and system to optimally route telephone calls between shared service centers is presented. Using a combination of service tiers, Agent Directory, Instant Messaging (IM), and Voice over Internet Protocol (VoIP) provides optimal routing of incoming calls for assistance. The method utilizes different protocols during normal operations, transitional operations, and emergency operations, and addresses Shared Service Center (SSC) planning and management.
Abstract:
A method and apparatus for performing packet classification in a digital signal processor for policy-based packet routing. For one embodiment, the digital signal processor includes a policy statement table for storing policy statements. Each policy statement has associated with it a priority number that indicates the priority of the policy statement relative to other policy statements. The priority numbers are separately stored in a priority index table. The priority index table includes priority logic that determines the most significant priority number from among the policy statements that match an incoming packet during a classification of filter operation. The priority logic also identifies the location in the priority index table of the most significant priority number. The identified location in the priority index table can be used to access associated route information or other information stored in a route memory array. New policy statements can be added at any location in the policy statement table, and the associated priority numbers loaded into corresponding locations in the priority index table. Priority numbers of previously stored priority policy statements may be updated such that the new policy statement does not have the same priority number as the previously stored policy statements.
Abstract:
A method and apparatus for performing packet classification in a digital signal processor for policy-based packet routing. For one embodiment, the digital signal processor includes a policy statement table for storing policy statements. Each policy statement has associated with it a priority number that indicates the priority of the policy statement relative to other policy statements. The priority numbers are separately stored in a priority index table. The priority index table includes priority logic that determines the most significant priority number from among the policy statements that match an incoming packet during a classification of filter operation. The priority logic also identifies the location in the priority index table of the most significant priority number. The identified location in the priority index table can be used to access associated route information or other information stored in a route memory array. New policy statements can be added at any location in the policy statement table, and the associated priority numbers loaded into corresponding locations in the priority index table. Priority numbers of previously stored priority policy statements may be updated such that the new policy statement does not have the same priority number as the previously stored policy statements.
Abstract:
A digital signal processor. The digital signal processor includes a first data classification block. The first data classification block outputs a first block priority number associated with a first data stored in the first data classification block that matches a search key. The digital signal processor includes a second data classification block. The second data classification block outputs a second priority number associated with a second data stored in the second data classification block that matches the search key. The digital signal processor includes a device index processor. The device index processor selects a most significant block priority number from the first block priority number and the second block priority number.
Abstract:
A computer system and method for capture and handling job listings obtained from various often unrelated corporate and job board postings via the internet for examination by a job searcher. This system includes a scraping module having one or more scraping engines operable to scrape job information data set from job listings on the corporate career sites and job boards, wherein the scraping module receives and stores the scraped job information data set in a database. The system also has a scraping management interface module coordinating operation of and communication between the scraping engines and the career sites and job boards, a scraped listing quality management module coupled to the scraping management interface module analyzing selected scraped job information data stored in the database, and a job categorization module that examines and categorizes each job information stored in the database into one or more of a predetermined set of categories and returns categorized job information to the database, and an extractor module communicating with the database for compiling and transferring categorized job information data from the database to a search bank. The search bank is then accessible by a job searcher through a job search client server cluster connected to the Internet.