Abstract:
Present embodiments describe a CAM device having a segmented CAM array. Each segment of the CAM array, or cell blocks, includes one or more rows of CAM cells. One or more of the cell blocks in the CAM array are selectively enabled during a search operation based on a detected matching condition of another cell block. By selectively enabling cell blocks during search operations only when needed, energy consumption is reduced. Selectively enabling a cell block includes selectively pre-charging match lines to the cell block, selectively enabling word lines to the cell block, and selectively enabling comparand line to the cell block. In accordance with certain embodiments, the CAM device is configurable to perform search operations in a pipelined manner. Accordingly, the CAM device is capable of performing multiple search operations simultaneously.
Abstract:
A content search system includes CAM device, a compiler, and an image loader. The CAM device, which includes a plurality of rows of CAM cells and a number of counter circuits selectively interconnected by a programmable interconnect structure (PRS), performs regular expression search operations. The compiler selectively converts the regular expression into a number of various bit groups, and the image loader loads corresponding bit groups into the CAM cells, into a number of memory elements that control configuration of the PRS, and into the counter circuits.
Abstract:
A content addressable memory (CAM) device having any number of rows, each of the rows including a match line connected to a plurality of CAM cells, a match line detector circuit, and a pre-charge circuit. The detector circuit detects a voltage of the match line and generates a feedback signal based on the detected match line voltage. The pre-charge circuit adaptively charges the match line in response to the feedback signal.
Abstract:
A content addressable memory (CAM) device includes a CAM array, a programmable interconnect structure, and a priority encoder. The CAM array includes a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates a match result for the CAM row. The programmable interconnect structure is coupled to each CAM row and a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates match results for the row. The programmable interconnect structure coupled to each CAM row, and is configured to logically connect any number N of selected CAM rows together to form a data word chain spanning N rows, regardless of whether the selected CAM rows are contiguous.
Abstract:
A computer system and method for capture, managing and presenting data obtained from various often unrelated postings via the Internet for examination by a user. This system includes a scraping module having one or more scraping engines operable to scrape information data sets from listings on the corporate sites and web sites, direct feeds, and other sources, wherein the scraping module receives and stores the scraped listing information data sets in a database. The system also has a management platform coordinating all operation of and communication between the sources, system administrators and processing modules. The processing modules in the platform include scraping management module analyzing selected scraped data stored in the database, and a categorization module that examines and categorizes each data set stored in the database into one or more of a predetermined set of categories and returns categorized data sets to the database.
Abstract:
A content addressable memory (CAM) device includes a plurality of CAM rows, a number of sequencing logic circuits, and a programmable interconnect structure. Each CAM row includes a number of CAM cells to generate a match signal on a match line and includes an enable input. Each sequencing logic circuit includes an input and an output, and is configured to count sequences of match signals from the CAM rows. The programmable interconnect structure selectively connects the match line of any CAM row to the input of any sequencing logic circuit, and selectively connects the output of any sequencing logic circuit to the enable input of any CAM row.
Abstract:
A system for searching an input string for a number of regular expressions includes a search block and a compiler. The search block includes a plurality of content addressable memory (CAM) devices, wherein each of the CAM devices is differently configured to implement search operations for regular expressions having a unique level of complexity. The compiler is configured to determine the complexity level of each of the regular expressions, and is configured to store each regular expression in a selected one of the CAM devices according to its complexity level.
Abstract:
A traffic management processor for processing different types of traffic flows includes a departure time calculator (DTC) circuit for calculating a departure time for each packet received, a content addressable memory (CAM) device coupled to the DTC circuit and having a plurality of rows, each row including a first portion for storing the departure time for a corresponding packet and including a second portion for storing a bit indicating a traffic type for the packet, and compare logic coupled to the CAM device and configured to determine which of the departure times stored in the CAM device is the earliest.
Abstract:
A content addressable memory (CAM) device having CAM cells arranged in rows and columns. A plurality of first data line pairs extend along respective columns of the CAM cells. A plurality of second data line pairs extend along respective columns of the CAM array adjacent the first data line pairs, each second data line pair having a first and second constituent data lines that cross one another at a point along their lengths.
Abstract:
A traffic management processor configured to selectively terminate individual traffic flows includes an instruction decoder to receive a termination instruction specifying which traffic flows are to be deleted, and a content addressable memory device having a plurality of rows, each including a flow ID and termination bit for a corresponding packet.