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公开(公告)号:US5065219A
公开(公告)日:1991-11-12
申请号:US697621
申请日:1991-05-09
申请人: Tomohide Terashima
发明人: Tomohide Terashima
IPC分类号: H01L21/74 , H01L21/336 , H01L21/76 , H01L21/762 , H01L21/8222 , H01L27/06 , H01L27/088 , H01L29/41 , H01L29/78
CPC分类号: H01L21/76297 , H01L27/088 , H01L29/7809
摘要: An n.sup.+ -type diffusion region (19) is formed in a surface of an n.sup.- -type semiconductor island (11) corresponding to a protrusion (23) by selective diffusion so that the bottom thereof is in contact with an n.sup.+ -type semiconductor layer (12) surrounding the island (11). A drain electrode (22) is formed on the diffusion region (19) to extract an operating current of a VDMOS transistor flowing through the n.sup.+ -type semiconductor layer (12). By virtue of the protrusion (23), the diffusion region (19) can reach the n.sup.+ -type semiconductor layer (12) by not so deep diffusion. Thus, lateral diffusion can be suppressed so that an area required for the diffusion region (19) may be smaller.
摘要翻译: 通过选择性扩散在n型半导体岛(11)的与突起(23)对应的表面上形成n +型扩散区(19),使其底部与n +型半导体层 (12)围绕岛(11)。 在扩散区(19)上形成漏电极(22),以提取流过n +型半导体层(12)的VDMOS晶体管的工作电流。 通过突起(23),扩散区域(19)可以通过不那么深的扩散而到达n +型半导体层(12)。 因此,可以抑制横向扩散,使得扩散区域(19)所需的面积可以更小。