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公开(公告)号:US20180331226A1
公开(公告)日:2018-11-15
申请号:US16033288
申请日:2018-07-12
IPC分类号: H01L29/78 , H01L29/66 , H01L29/423 , H01L29/10 , H01L29/08 , H01L29/06 , H01L27/088 , H01L21/8234 , H01L21/266 , H01L21/265 , H01G4/33 , H01G4/30 , H01G4/228 , H01G4/14 , H01G4/005 , B32B27/36 , B32B27/34 , B32B27/32 , B32B27/30 , B32B27/28 , B32B27/08 , B32B27/00 , B32B7/02 , B32B3/08 , B29C47/56 , B29C47/06 , B29C37/00 , B29K23/00 , B29L31/34 , B29L9/00 , B29K507/04 , B29K105/16
CPC分类号: H01L27/0886 , B29C37/0025 , B29C47/065 , B29C47/56 , B29K2023/12 , B29K2105/16 , B29K2507/04 , B29K2995/0005 , B29K2995/0007 , B29L2009/003 , B29L2009/005 , B29L2031/34 , B32B3/08 , B32B7/02 , B32B27/00 , B32B27/08 , B32B27/28 , B32B27/306 , B32B27/308 , B32B27/32 , B32B27/34 , B32B27/36 , B32B2262/106 , B32B2264/105 , B32B2264/12 , B32B2270/00 , B32B2274/00 , B32B2307/202 , B32B2307/204 , B32B2307/206 , B32B2307/518 , B32B2307/732 , B32B2457/16 , H01G4/005 , H01G4/14 , H01G4/228 , H01G4/30 , H01G4/33 , H01L21/26513 , H01L21/266 , H01L21/823412 , H01L21/823431 , H01L21/823475 , H01L21/823481 , H01L21/823493 , H01L29/0649 , H01L29/0653 , H01L29/0657 , H01L29/0696 , H01L29/086 , H01L29/0865 , H01L29/0869 , H01L29/0882 , H01L29/0886 , H01L29/1045 , H01L29/1095 , H01L29/4236 , H01L29/42376 , H01L29/4238 , H01L29/42392 , H01L29/66681 , H01L29/66704 , H01L29/66712 , H01L29/66734 , H01L29/66795 , H01L29/7802 , H01L29/7809 , H01L29/7811 , H01L29/7816 , H01L29/7825 , H01L29/7851 , H01L29/7856 , H01L2029/7858
摘要: A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.
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公开(公告)号:US10062777B2
公开(公告)日:2018-08-28
申请号:US15485892
申请日:2017-04-12
发明人: Marie Denison , Sameer Pendharkar , Guru Mathur
CPC分类号: H01L29/7813 , H01L21/225 , H01L21/283 , H01L21/324 , H01L21/823487 , H01L29/063 , H01L29/0696 , H01L29/0878 , H01L29/0882 , H01L29/1095 , H01L29/404 , H01L29/407 , H01L29/408 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/51 , H01L29/511 , H01L29/517 , H01L29/518 , H01L29/66734 , H01L29/7809
摘要: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.
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公开(公告)号:US09923073B2
公开(公告)日:2018-03-20
申请号:US15423112
申请日:2017-02-02
申请人: ROHM CO., LTD.
发明人: Yuki Nakano , Ryota Nakamura
IPC分类号: H01L29/94 , H01L29/423 , H01L29/78 , H01L29/06 , H01L29/417 , H01L29/49 , H01L29/10 , H01L29/16 , H01L29/20 , H01L29/36 , H01L29/51 , H01L29/40
CPC分类号: H01L29/4236 , H01L29/0619 , H01L29/0649 , H01L29/0657 , H01L29/0661 , H01L29/0688 , H01L29/0692 , H01L29/0696 , H01L29/1095 , H01L29/1602 , H01L29/1608 , H01L29/2003 , H01L29/36 , H01L29/402 , H01L29/407 , H01L29/41766 , H01L29/42372 , H01L29/42376 , H01L29/4238 , H01L29/4916 , H01L29/4925 , H01L29/4958 , H01L29/518 , H01L29/7809 , H01L29/7811 , H01L29/7813
摘要: A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, and a surface insulating film disposed in a manner extending across the cell portion and the outer peripheral portion, and in the cell portion, formed to be thinner than a part in the outer peripheral portion.
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公开(公告)号:US20170365704A1
公开(公告)日:2017-12-21
申请号:US15632199
申请日:2017-06-23
发明人: Hideaki Tsuchiko
IPC分类号: H01L29/78 , H01L29/66 , H01L29/417 , H01L29/40 , H01L21/306 , H01L27/092 , H01L27/088 , H01L21/8234 , H01L21/265 , H01L29/08 , H01L29/06
CPC分类号: H01L29/7802 , H01L21/265 , H01L21/30604 , H01L21/823418 , H01L21/823493 , H01L27/088 , H01L27/0922 , H01L27/0928 , H01L29/0653 , H01L29/0847 , H01L29/086 , H01L29/0878 , H01L29/407 , H01L29/41741 , H01L29/41766 , H01L29/66659 , H01L29/66712 , H01L29/66719 , H01L29/7809 , H01L29/7835
摘要: A transistor includes a semiconductor body; a body region of a first conductivity type formed in the semiconductor body; a gate electrode formed partially overlapping the body region and insulated from the semiconductor body by a gate dielectric layer; a source region of a second conductivity type formed in the body region on a first side of the gate electrode; a trench formed in the semiconductor body on a second side of the gate electrode, the trench being lined with a sidewall dielectric layer and filled with a bottom dielectric layer and a conductive layer above the bottom dielectric layer, the conductive layer being electrically connected to the gate electrode; and a doped sidewall region of the second conductivity type formed in the semiconductor body along the sidewall of the trench where the doped sidewall region forms a vertical drain current path for the transistor.
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公开(公告)号:US09818859B2
公开(公告)日:2017-11-14
申请号:US13219283
申请日:2011-08-26
申请人: Chi-Chih Chen , Kun-Hsuan Tien , Ruey-Hsin Liu
发明人: Chi-Chih Chen , Kun-Hsuan Tien , Ruey-Hsin Liu
IPC分类号: H01L29/78 , H01L21/336 , H01L29/66 , H01L29/417 , H01L29/423 , H01L29/08
CPC分类号: H01L29/7809 , H01L29/0878 , H01L29/41766 , H01L29/41775 , H01L29/42368 , H01L29/42376 , H01L29/66734
摘要: A MOSFET includes a semiconductor substrate having a top surface, a body region of a first conductivity type in the semiconductor substrate, and a double diffused drain (DDD) region having a top surface lower than a bottom surface of the body region. The DDD region is of a second conductivity type opposite the first conductivity type. The MOSFET further includes a gate oxide, and a gate electrode separated from the body region by the gate oxide. A portion of the gate oxide and a portion of the gate electrode are below the top surface of the body region.
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公开(公告)号:US20170309742A1
公开(公告)日:2017-10-26
申请号:US15646968
申请日:2017-07-11
发明人: Po-Yu Chen
IPC分类号: H01L29/78 , H01L21/265 , H01L29/66 , H01L29/10 , H01L29/08 , H01L29/06 , H01L27/12 , H01L21/762 , H01L29/786
CPC分类号: H01L29/7809 , H01L21/26513 , H01L21/76232 , H01L21/76283 , H01L27/1203 , H01L29/0653 , H01L29/0865 , H01L29/0882 , H01L29/1037 , H01L29/1095 , H01L29/66704 , H01L29/66712 , H01L29/66734 , H01L29/7812 , H01L29/7813 , H01L29/7824 , H01L29/7825 , H01L29/78642
摘要: A lateral trench MOSFET comprises an insulating layer buried in a substrate, a body region in the substrate, an isolation region in the substrate, a first drain/source region over the body region, a second drain/source region in the substrate, wherein the first drain/source region and the second drain/source region are on opposing sides of the isolation region, a drift region comprising a first drift region of a first doping density formed between the second drain/source region and the insulating layer, wherein the first drift region comprises an upper portion surrounded by isolation regions and a lower portion and a second drift region of a second doping density formed between the isolation region and the insulating layer, wherein a height of the second drift region is equal to a height of the lower portion of the first drift region.
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公开(公告)号:US20170207341A1
公开(公告)日:2017-07-20
申请号:US15474096
申请日:2017-03-30
CPC分类号: H01L29/7856 , B29C37/0025 , B29C47/065 , B29C47/56 , B29K2023/12 , B29K2105/16 , B29K2507/04 , B29K2995/0005 , B29K2995/0007 , B29L2009/003 , B29L2009/005 , B29L2031/34 , B32B3/08 , B32B7/02 , B32B27/00 , B32B27/08 , B32B27/28 , B32B27/306 , B32B27/308 , B32B27/32 , B32B27/34 , B32B27/36 , B32B2262/106 , B32B2264/105 , B32B2264/12 , B32B2270/00 , B32B2274/00 , B32B2307/202 , B32B2307/204 , B32B2307/206 , B32B2307/518 , B32B2307/732 , B32B2457/16 , H01G4/005 , H01G4/14 , H01G4/228 , H01G4/30 , H01G4/33 , H01L21/26513 , H01L21/266 , H01L21/823412 , H01L21/823431 , H01L21/823475 , H01L21/823481 , H01L21/823493 , H01L27/0886 , H01L29/0649 , H01L29/0653 , H01L29/0657 , H01L29/0696 , H01L29/086 , H01L29/0865 , H01L29/0869 , H01L29/0882 , H01L29/0886 , H01L29/1045 , H01L29/1095 , H01L29/4236 , H01L29/42376 , H01L29/4238 , H01L29/42392 , H01L29/66681 , H01L29/66704 , H01L29/66712 , H01L29/66734 , H01L29/66795 , H01L29/7802 , H01L29/7809 , H01L29/7811 , H01L29/7816 , H01L29/7825 , H01L29/7851 , H01L2029/7858
摘要: A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.
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公开(公告)号:US09680002B2
公开(公告)日:2017-06-13
申请号:US15193718
申请日:2016-06-27
发明人: Sam Ziqun Zhao , Frank Hui
CPC分类号: H01L29/7809 , H01L29/0653 , H01L29/0843 , H01L29/1033 , H01L29/1037 , H01L29/66666 , H01L29/66712 , H01L29/781 , H01L29/7827
摘要: Semiconductor devices and manufacturing methods are provided for making channel and gate lengths independent from lithography. Also, semiconductor devices and manufacturing methods are provided for increasing resistivity between drain and channel to allow for higher voltage operation. For example, a semiconductor device includes a first doped layer implanted in a semiconductor substrate forming one of a source or a drain and a gate metal layer disposed over the first doped layer. The semiconductor device further includes a second doped layer disposed over the gate metal forming the other the source or the drain, where the first doped layer, the gate metal layer and the second doped layer form a vertical stack of layers of the semiconductor device. The semiconductor device further includes a conduction channel formed in a trench that extends vertically through the vertical stack of layers and terminates at the semiconductor substrate.
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公开(公告)号:US09653455B1
公开(公告)日:2017-05-16
申请号:US14937627
申请日:2015-11-10
发明人: Edward John Coyne
IPC分类号: H01L27/06 , H01L29/08 , H01L29/73 , H01L29/78 , H01L29/417 , H01L29/66 , H01L21/8234
CPC分类号: H01L27/0623 , H01L21/823475 , H01L27/0705 , H01L27/1203 , H01L29/0804 , H01L29/0821 , H01L29/41741 , H01L29/41766 , H01L29/66234 , H01L29/66666 , H01L29/7302 , H01L29/7802 , H01L29/7803 , H01L29/7809 , H01L29/7813 , H01L29/7827
摘要: A transistor switch device is provided that exhibits relatively good voltage capability and relatively easy drive requirements to turn the device on and off. This can reduce transient drive current flows that may perturb other components.
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公开(公告)号:US20170125598A1
公开(公告)日:2017-05-04
申请号:US15402504
申请日:2017-01-10
CPC分类号: H01L29/7856 , B29C37/0025 , B29C47/065 , B29C47/56 , B29K2023/12 , B29K2105/16 , B29K2507/04 , B29K2995/0005 , B29K2995/0007 , B29L2009/003 , B29L2009/005 , B29L2031/34 , B32B3/08 , B32B7/02 , B32B27/00 , B32B27/08 , B32B27/28 , B32B27/306 , B32B27/308 , B32B27/32 , B32B27/34 , B32B27/36 , B32B2262/106 , B32B2264/105 , B32B2264/12 , B32B2270/00 , B32B2274/00 , B32B2307/202 , B32B2307/204 , B32B2307/206 , B32B2307/518 , B32B2307/732 , B32B2457/16 , H01G4/005 , H01G4/14 , H01G4/228 , H01G4/30 , H01G4/33 , H01L21/26513 , H01L21/266 , H01L21/823412 , H01L21/823431 , H01L21/823475 , H01L21/823481 , H01L21/823493 , H01L27/0886 , H01L29/0649 , H01L29/0653 , H01L29/0657 , H01L29/0696 , H01L29/086 , H01L29/0865 , H01L29/0869 , H01L29/0882 , H01L29/0886 , H01L29/1045 , H01L29/1095 , H01L29/4236 , H01L29/42376 , H01L29/4238 , H01L29/42392 , H01L29/66681 , H01L29/66704 , H01L29/66712 , H01L29/66734 , H01L29/66795 , H01L29/7802 , H01L29/7809 , H01L29/7811 , H01L29/7816 , H01L29/7825 , H01L29/7851 , H01L2029/7858
摘要: A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.
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