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139 条记录 (耗时 0.028 秒)

    ENHANCING PERFORMANCE BY INSTRUCTION INTERLEAVING AND/OR CONCURRENT PROCESSING OF MULTIPLE BUFFERS
    92.
    发明申请
    ENHANCING PERFORMANCE BY INSTRUCTION INTERLEAVING AND/OR CONCURRENT PROCESSING OF MULTIPLE BUFFERS 有权
    通过指令交互和/或多个缓冲区的并发处理来提高性能

    公开(公告)号：US20120151183A1

    公开(公告)日：2012-06-14

    申请号：US12963298

    申请日：2010-12-08

    申请人： James D. Guilford ,  Wajdi K. Feghali ,  Vinodh Gopal ,  Gilbert M. Wolrich ,  Erdinc Ozturk ,  Martin G. Dixon ,  Deniz Karakoyunlu ,  Kahraman D. Akdemir

    发明人： James D. Guilford ,  Wajdi K. Feghali ,  Vinodh Gopal ,  Gilbert M. Wolrich ,  Erdinc Ozturk ,  Martin G. Dixon ,  Deniz Karakoyunlu ,  Kahraman D. Akdemir

    IPC分类号： G06F9/38 ,  G06F9/46

    CPC分类号： G06F9/3851 ,  G06F9/30109 ,  G06F9/4843

    摘要： An embodiment may include circuitry to execute, at least in part, a first list of instructions and/or to concurrently process, at least in part, first and second buffers. The execution of the first list of instructions may result, at least in part, from invocation of a first function call. The first list of instructions may include at least one portion of a second list of instructions interleaved, at least in part, with at least one other portion of a third list of instructions. The portions may be concurrently carried out, at least in part, by one or more sets of execution units of the circuitry. The second and third lists of instructions may implement, at least in part, respective algorithms that are amenable to being invoked by separate respective function calls. The concurrent processing may involve, at least in part, complementary algorithms.

    摘要翻译： 实施例可以包括至少部分地执行第一指令列表和/或至少部分地执行第一和第二缓冲器的电路。 第一指令列表的执行可以至少部分地由第一函数调用的调用产生。 第一指令列表可以包括至少部分地与第三指令列表的至少一个其他部分交织的第二指令列表的至少一部分。 这些部分可以至少部分地由电路的一个或多个执行单元同时执行。 第二和第三指令列表可以至少部分地实现适合于通过单独的各自的功能调用来调用的相应算法。 并行处理可以至少部分地涉及互补算法。

    Configurable exponent FIFO
    96.
    发明授权
    Configurable exponent FIFO 有权
    可配置指数FIFO

    公开(公告)号：US07912886B2

    公开(公告)日：2011-03-22

    申请号：US11610841

    申请日：2006-12-14

    申请人： Vinodh Gopal ,  Wajdi Feghali ,  Gilbert M. Wolrich ,  Daniel Cutter ,  Robert P. Ottavi

    发明人： Vinodh Gopal ,  Wajdi Feghali ,  Gilbert M. Wolrich ,  Daniel Cutter ,  Robert P. Ottavi

    IPC分类号： G06F7/38 ,  H04K1/00 ,  H04L9/00 ,  H04L9/30

    CPC分类号： G06F7/723

    摘要： The present disclosure provides a system and method for performing modular exponentiation. The method includes loading a first word of a vector from memory into a first register and subsequently loading the first word from the first register to a second register. The method may also include loading a second word into the first register and loading at least one bit from the second register into an arithmetic logic unit. The method may further include performing modular exponentiation on the at least one bit to generate a result and generating a public key based upon, at least in part, the result. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

    摘要翻译： 本公开提供了一种用于执行模幂运算的系统和方法。 该方法包括将来自存储器的向量的第一字加载到第一寄存器中，并随后将第一个字从第一寄存器加载到第二寄存器。 该方法还可以包括将第二字加载到第一寄存器中并将至少一个比特从第二寄存器加载到算术逻辑单元中。 该方法还可以包括在至少一个比特上执行模幂运算以产生结果，并且至少部分地基于结果生成公开密钥。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

    Storage accelerator
    97.
    发明授权
    Storage accelerator 有权
    存储加速器

    公开(公告)号：US07797612B2

    公开(公告)日：2010-09-14

    申请号：US11617966

    申请日：2006-12-29

    申请人： Vinodh Gopal ,  Yogesh Bansal ,  Gilbert M. Wolrich ,  Wajdi Feghali ,  Kirk Yap

    发明人： Vinodh Gopal ,  Yogesh Bansal ,  Gilbert M. Wolrich ,  Wajdi Feghali ,  Kirk Yap

    IPC分类号： G11C29/00

    CPC分类号： G06F11/1076 ,  G06F2211/1057

    摘要： The present disclosure provides a method for generating RAID syndromes. In one embodiment the method may include loading a first data byte of a first disk block and a first data byte of a second disk block from a storage device to an arithmetic logic unit. The method may further include XORing the first data byte of the first disk block and the first data byte of the second disk block to generate a first result and storing the first result in a results buffer. The method may also include iteratively repeating, loading intermediate data bytes corresponding to the first disk block and intermediate data bytes corresponding to the second disk block from the storage device to the arithmetic logic unit. The method may additionally include XORing the intermediate data bytes corresponding to the first disk block and the intermediate data bytes corresponding to the second disk block to generate intermediate results and generating a RAID syndrome based on, at least in part, the intermediate results. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

    摘要翻译： 本公开提供了一种用于生成RAID综合征的方法。 在一个实施例中，该方法可以包括将第一磁盘块的第一数据字节和第二磁盘块的第一数据字节从存储设备加载到算术逻辑单元。 该方法还可以包括将第一磁盘块的第一数据字节和第二磁盘块的第一数据字节进行异或，以产生第一结果并将第一结果存储在结果缓冲器中。 该方法还可以包括将对应于第一磁盘块的中间数据字节和对应于第二磁盘块的中间数据字节从存储设备反复重复加载到算术逻辑单元。 该方法还可以包括对与第一磁盘块相对应的中间数据字节和对应于第二磁盘块的中间数据字节进行异或，以产生中间结果，并至少部分地基于中间结果生成RAID综合征。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

    Multi-threaded sequenced receive for fast network port stream of packets
    99.
    发明授权
    Multi-threaded sequenced receive for fast network port stream of packets 有权
    多线程排序接收快速网络端口流数据包

    公开(公告)号：US07434221B2

    公开(公告)日：2008-10-07

    申请号：US11239547

    申请日：2005-09-28

    申请人： Donald F. Hooper ,  Matthew J. Adiletta ,  Gilbert M. Wolrich

    发明人： Donald F. Hooper ,  Matthew J. Adiletta ,  Gilbert M. Wolrich

    IPC分类号： G06F9/46

    CPC分类号： G06F9/546 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/485 ,  G06F9/4881 ,  G06F9/544

    摘要： A method of processing network data in a network processor includes using three or more threads to process a beginning portion, a middle portion, and an end portion of data packet is presented. The first thread processes the beginning portion; one or more middle threads process the middle portion, and a last thread processes the end portion. First information is indirectly passed from the first thread to the last thread via a first buffer with the middle threads progressively updating the first information. Second information is directly passed from the first thread to the last thread via a second buffer.

    摘要翻译： 一种在网络处理器中处理网络数据的方法包括使用三个或更多个线程来处理数据分组的开始部分，中间部分和结束部分。 第一个线程处理起始部分; 一个或多个中间线程处理中间部分，最后一个线程处理端部。 第一个信息通过第一个缓冲区从第一个线程间接传递到最后一个线程，中间线程逐渐更新第一个信息。 第二个信息通过第二个缓冲区从第一个线程直接传递到最后一个线程。

    Method for Processing Multiple Operations
    100.
    发明申请
    Method for Processing Multiple Operations 有权
    多操作处理方法

    公开(公告)号：US20080159528A1

    公开(公告)日：2008-07-03

    申请号：US11617418

    申请日：2006-12-28

    申请人： Wajdi Feghali ,  Stephanie Hirnak ,  Makaram Raghunandan ,  Yogesh Bansal ,  Kirk Yap ,  Gilbert M. Wolrich

    发明人： Wajdi Feghali ,  Stephanie Hirnak ,  Makaram Raghunandan ,  Yogesh Bansal ,  Kirk Yap ,  Gilbert M. Wolrich

    IPC分类号： H04L9/30 ,  H04L9/28

    CPC分类号： H04L63/0485 ,  G06F9/30181 ,  G06F9/3879 ,  H04L63/08

    摘要： In one embodiment, the present disclosure provides a method capable of processing a variety of different operations. A method according to one embodiment may include loading configuration data from a shared memory unit into a hardware configuration register, the hardware configuration register located within circuitry included within a hardware accelerator unit. The method may also include issuing a command set from a microengine to the hardware accelerator unit having the circuitry. The method may additionally include receiving the command set at the circuitry from the microengine, the command set configured to allow for the processing of a variety of different operations. The method may further include processing an appropriate operation based upon the configuration data loaded into the hardware configuration register. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

    摘要翻译： 在一个实施例中，本公开提供了一种能够处理各种不同操作的方法。 根据一个实施例的方法可以包括将配置数据从共享存储器单元加载到硬件配置寄存器中，硬件配置寄存器位于包括在硬件加速器单元内的电路内。 该方法还可以包括从微引擎向具有该电路的硬件加速器单元发出命令集。 该方法可以另外包括接收来自微引擎的电路处的命令集，该命令集被配置为允许处理各种不同的操作。 该方法还可以包括基于加载到硬件配置寄存器中的配置数据来处理适当的操作。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。