Asynchronous data movement pipeline

    公开(公告)号:US12118382B2

    公开(公告)日:2024-10-15

    申请号:US17671490

    申请日:2022-02-14

    CPC classification number: G06F9/485 G06F9/524 G06F9/544

    Abstract: Apparatuses, systems, and techniques to parallelize operations in one or more programs with data copies from global memory to shared memory in each of the one or more programs. In at least one embodiment, a program performs operations on shared data and then asynchronously copies shared data to shared memory, and continues performing additional operations in parallel while the shared data is copied to shared memory until an indicator provided by an application programming interface to facilitate parallel computing, such as CUDA, informs said program that shared data has been copied to shared memory.

    Geospatial data workflow platform

    公开(公告)号:US12086629B1

    公开(公告)日:2024-09-10

    申请号:US17371580

    申请日:2021-07-09

    CPC classification number: G06F9/485 G06F21/6218

    Abstract: Executing geospatial data workflows includes receiving a representation of a first workflow. It further includes receiving a request to execute a second workflow, the second workflow including a reference to the first workflow. At least one of the first workflow and the second workflow comprises at least one geospatial transformation operation. It further includes determining that the first workflow referenced by the second workflow is permitted to be accessed. It further includes, based at least in part on determining that the first workflow is permitted to be accessed, executing the second workflow, including executing the representation of the first workflow comprising the at least one geospatial transformation operation.

    Fractional force-quit for reconfigurable processors

    公开(公告)号:US12073231B2

    公开(公告)日:2024-08-27

    申请号:US17974496

    申请日:2022-10-26

    Inventor: Manish K. Shah

    CPC classification number: G06F9/442 G06F9/485 G06F15/16 G06F15/80

    Abstract: A reconfigurable data processor includes an array of configurable units. The array includes a two or more sub-arrays of configurable units, and sub-arrays of configurable units in the plurality of sub-arrays of configurable units are configurable to separately execute different programs. The reconfigurable data processor also includes a force-quit controller connected to the array. The force-quit controller can stop execution of a particular program on a particular sub-array of configurable units and reset the particular sub-array of configurable units, while remaining sub-arrays of configurable units continue execution of their respective programs.

Patent Agency Ranking