Abstract:
In one embodiment, an audio-visual content delivery system, such as a set-top box/personal video recorder system, is configured to interface with a local area network (LAN). A packet processing circuit comprised in the system may be configured to filter and route Ethernet packet data received from the LAN to specific ports and/or queues without host processor intervention. The packet processing circuit may utilize a set of filter and routing mechanisms configurable in hardware to interpret various Internet Engineering Task Force (IETF) networking transport protocols, and may transfer the packet data in a format recognized by a variety of consumer subsystems, each of which may be coupled to the decoder. The packet processing circuit may be implemented as a semiconductor device, and may allow encapsulated application data, (encapsulated using standardized encapsulation techniques), to be routed to a plurality of different types of application sinks or processors, forming a point-to-point or multi-point serial or parallel data stream over a standard transport covering numerous levels of the ISO data communications stack.
Abstract:
A system and method for measuring the speed of a fan in an electrical system is presented. The duty cycle of a pulse width modulated (PWM) signal provided by a signal generator may control the speed of the fan. The fan may generate tachometer pulses that may be used by a tachometer reading-unit to monitor the RPM of the fan. Very low frequency test (VLFT) pulses may be generated and provided through a sampling signal multiplexed with the PWM signal to sample the fan generated tachometer pulses even when the PWM signal is low. The frequency of the sampling signal may be determined based on the duty cycle of the PWM signal and may be dynamically updated when the duty cycle of the PWM signal is updated. The sampling signal may be used as the clock input to a flip-flop with the tachometer pulses as the data input, and the output of the flip-flop providing an input to a pulse counter that counts the number of pulses within a determined period of time, providing as its output the measured RPM of the fan.
Abstract:
A system and method for generating a test signal used in measuring the speed of a rotating device, such as a fan in a computer system is disclosed. A pulse width modulated (PWM) signal may power the fan with the duty cycle of the PWM signal controlling the speed of the fan. The fan may generate tachometer pulses used for monitoring RPM of the fan. The frequency of the test signal may be selected to be at least twice the frequency of the tachometer pulses. The test signal may be generated from a base frequency signal using two cascaded frequency dividers. The first divider may output a scaled base frequency signal obtained by dividing the base frequency signal by a user programmable scale frequency coefficient corresponding to a maximum test signal frequency for the fan. The second divider may output the test signal by dividing the scaled base frequency signal by a fraction frequency coefficient obtained from and proportional to the current PWM duty cycle value. The test signal may be multiplexed with the PWM signal to obtain existing tachometer pulses even when the PWM signal is not asserted. The scale frequency coefficient may only need to be programmed once for each fan.
Abstract:
A system and method for controlling a fan is disclosed. A single control signal value for controlling the fan, such as a single PWM duty cycle value for a corresponding PWM generator output powering the fan, may be calculated by combining sensor data from two or more temperature zones. In one embodiment, the single PWM duty cycle value may be determined based on the temperature in a first zone, for example the CPU, with an additional factor based on the temperature in a second zone, for example the ambient temperature of a PC enclosure. In one embodiment, the final single PWM value is determined by adding an offset value to a PWM value calculated based on the current temperature of the first zone, where the offset value is obtained by calculating a first ΔPWM factor for the first zone, and using the first ΔPWM factor, in conjunction with a scaling factor, to weight a second ΔPWM factor calculated for the second zone.
Abstract:
Various embodiments of a voltage level detector implemented as an integrated circuit whose trip point is approximately constant over variations in temperature as well as variations in transistor fabrication parameters are disclosed along with a differential amplifier whose input offset voltage is highly immune to said variations. In one embodiment, a voltage generator supplies a composite voltage to the gate of the tail current transistor of the voltage level detector or differential amplifier. The first component of the voltage is approximately equal to the threshold voltage of NMOS transistors comprised in the device over variations in operating temperature as well as variations in transistor fabrication parameters while the second component is approximately constant with respect to said variations. When applied to the gate of the tail current transistor, the first component may turn the transistor on in spite of the above-mentioned parametric variations.
Abstract:
A radio transmitter system designed using an FSK modulator with IQ up-mixers and sinewave coded digital-to-analog converters (DACs). The radio transmitter system may include a frequency shift keying (FSK) coding logic circuit coupled to the inputs of an IQ modulation and image reject up-mixer through a respective DAC and a respective low pass filter (LPF) for each the I and the Q channels. The FSK modulation scheme may employ sine and cosine signals for the I and Q channels, respectively, where the sine and cosine waves are directly coded into the DACs. The coded levels required by the DACs may be generated using current sources and may be Gray-coded. The output of the IQ modulation and image reject up-mixer may be connected to a power amplifier, which may be used to transmit the modulated RF signal via a loop antenna.
Abstract:
A memory alignment system for efficient data transfer between a host system and a remote system comprises a data communications controller configured to align transmitted and received data based on formatting information received from the host system. When transmitting data from local system memory, for example over an Ethernet connection, communications control driver software may first write formatting information corresponding to the data into a configurable transmit data buffer. The data communications controller is operable to align the data based on the formatting information as the driver software moves the data into the transmit data buffer. Similarly, the driver software may write formatting information for receive data into a receive-format configuration buffer. The data communications controller may align the receive data based on the receive-formatting information as the receive data is being written into a configurable receive buffer. As the data communications controller performs all the required data alignment, no data alignment by the host processor is required.
Abstract:
A temperature sensor circuit and system providing accurate readings using a temperature diode whose ideality factor may fall within a determined range. In one set of embodiments a change in diode junction voltage (ΔVBE) proportional to the temperature of the diode is captured and provided to an ADC, which may perform required signal conditioning functions on ΔVBE, and provide a numeric value output corresponding to the temperature of the diode. Errors in the measured temperature that might result from using diodes with ideality factors that differ from an expected ideality factor may be eliminated by programming the system to account for differing ideality factors. The gain of the temperature sensor may be matched to the ideality factor of the temperature diode by using an accurate, highly temperature stable reference voltage of the ADC to set the gain of the temperature measurement system. The reference voltage may have a trim capability to change the gain setting voltage by a digital address comprising a determined number of bits, with the programmable range for the reference voltage corresponding to a determined range of ideality factors.
Abstract:
In one embodiment, a system comprises a programming unit coupled to at least one programmable fuse and configured to program the programmable fuse. In addition, the system comprises a monitoring circuit coupled to the programmable fuse and configured to monitor electrical characteristics associated with the programmable fuse while the programmable fuse is being programmed. In one embodiment, the monitoring circuit is configured to detect a voltage associated with the programmable fuse. Furthermore, the monitoring circuit is configured to compare the detected voltage associated with the programmable fuse with a predetermined voltage value (i.e., endpoint detection). If the detected voltage is equal to or less than the predetermined voltage value, the monitoring circuit is configured to change a state of a control signal to stop the programming of the programmable fuse. Otherwise, the programming unit continues to program the programmable fuse.
Abstract:
A portable RAM drive comprising data stored on a non-volatile memory and transferable to a volatile memory when the portable RAM drive is coupled to a computer system. When the portable RAM drive is plugged into the computer system, the data from the non-volatile memory may be transferred to the volatile memory for faster access by the computer. If the portable RAM drive is unplugged from the computer, an internal power source may power the portable RAM drive long enough to transfer the data from the volatile memory to the non-volatile memory. In one embodiment, the portable RAM drive may use a restraining device or an indicator light to indicate to the user that the portable RAM drive should not be unplugged from the computer because the data has not yet been transferred from the volatile memory to the non-volatile memory.