High speed ethernet MAC and PHY apparatus with a filter based ethernet packet router with priority queuing and single or multiple transport stream interfaces
    101.
    发明申请
    High speed ethernet MAC and PHY apparatus with a filter based ethernet packet router with priority queuing and single or multiple transport stream interfaces 有权
    具有优先级排队和单个或多个传输流接口的基于过滤器的以太网分组路由器的高速以太网MAC和PHY设备

    公开(公告)号:US20060174032A1

    公开(公告)日:2006-08-03

    申请号:US11046292

    申请日:2005-01-28

    CPC classification number: H04L45/00 H04L12/4633 H04L12/6418 H04L47/2416

    Abstract: In one embodiment, an audio-visual content delivery system, such as a set-top box/personal video recorder system, is configured to interface with a local area network (LAN). A packet processing circuit comprised in the system may be configured to filter and route Ethernet packet data received from the LAN to specific ports and/or queues without host processor intervention. The packet processing circuit may utilize a set of filter and routing mechanisms configurable in hardware to interpret various Internet Engineering Task Force (IETF) networking transport protocols, and may transfer the packet data in a format recognized by a variety of consumer subsystems, each of which may be coupled to the decoder. The packet processing circuit may be implemented as a semiconductor device, and may allow encapsulated application data, (encapsulated using standardized encapsulation techniques), to be routed to a plurality of different types of application sinks or processors, forming a point-to-point or multi-point serial or parallel data stream over a standard transport covering numerous levels of the ISO data communications stack.

    Abstract translation: 在一个实施例中,诸如机顶盒/个人录像机系统的视听内容传送系统被配置为与局域网(LAN)进行接口。 包括在系统中的分组处理电路可以被配置为在没有主机处理器干预的情况下将从LAN接收到的以太网分组数据过滤并路由到特定端口和/或队列。 分组处理电路可以利用在硬件中配置的一组过滤器和路由机制来解释各种因特网工程任务组(IETF)网络传输协议,并且可以以各种消费者子系统识别的格式传送分组数据,每个消费者子系统 可以耦合到解码器。 分组处理电路可以被实现为半导体器件,并且可以允许封装的应用数据(使用标准封装技术封装)被路由到多个不同类型的应用接收器或处理器,形成点对点或 跨标准传输的多点串行或并行数据流,覆盖ISO数据通信堆栈的多个级别。

    Method and apparatus for generating accurate fan tachometer readings
    102.
    发明授权
    Method and apparatus for generating accurate fan tachometer readings 有权
    用于产生精确的风扇转速表读数的方法和装置

    公开(公告)号:US07076159B2

    公开(公告)日:2006-07-11

    申请号:US10637468

    申请日:2003-08-08

    Applicant: Len Bekker

    Inventor: Len Bekker

    CPC classification number: H02P7/29

    Abstract: A system and method for measuring the speed of a fan in an electrical system is presented. The duty cycle of a pulse width modulated (PWM) signal provided by a signal generator may control the speed of the fan. The fan may generate tachometer pulses that may be used by a tachometer reading-unit to monitor the RPM of the fan. Very low frequency test (VLFT) pulses may be generated and provided through a sampling signal multiplexed with the PWM signal to sample the fan generated tachometer pulses even when the PWM signal is low. The frequency of the sampling signal may be determined based on the duty cycle of the PWM signal and may be dynamically updated when the duty cycle of the PWM signal is updated. The sampling signal may be used as the clock input to a flip-flop with the tachometer pulses as the data input, and the output of the flip-flop providing an input to a pulse counter that counts the number of pulses within a determined period of time, providing as its output the measured RPM of the fan.

    Abstract translation: 提出了一种用于测量电气系统中风扇速度的系统和方法。 由信号发生器提供的脉宽调制(PWM)信号的占空比可以控制风扇的速度。 风扇可能会产生转速计脉冲,转速计读数单元可用于监视风扇转速。 可以通过与PWM信号多路复用的采样信号来生成和提供极低频测试(VLFT)脉冲,以便即使在PWM信号为低电平时对风扇产生的转速计脉冲进行采样。 可以基于PWM信号的占空比来确定采样信号的频率,并且可以在更新PWM信号的占空比时动态地更新采样信号的频率。 采样信号可以用作触发器的时钟输入,其中以转速计脉冲作为数据输入,并且触发器的输出向脉冲计数器提供输入,该脉冲计数器对在确定的周期内的脉冲数进行计数 时间,提供风扇测量的RPM的输出。

    Method and apparatus for accurate fan tachometer readings of PWM fans with different speeds
    103.
    发明授权
    Method and apparatus for accurate fan tachometer readings of PWM fans with different speeds 失效
    具有不同速度的PWM风扇精确风扇转速表读数的方法和装置

    公开(公告)号:US07069172B2

    公开(公告)日:2006-06-27

    申请号:US10843199

    申请日:2004-05-11

    CPC classification number: G01P3/48

    Abstract: A system and method for generating a test signal used in measuring the speed of a rotating device, such as a fan in a computer system is disclosed. A pulse width modulated (PWM) signal may power the fan with the duty cycle of the PWM signal controlling the speed of the fan. The fan may generate tachometer pulses used for monitoring RPM of the fan. The frequency of the test signal may be selected to be at least twice the frequency of the tachometer pulses. The test signal may be generated from a base frequency signal using two cascaded frequency dividers. The first divider may output a scaled base frequency signal obtained by dividing the base frequency signal by a user programmable scale frequency coefficient corresponding to a maximum test signal frequency for the fan. The second divider may output the test signal by dividing the scaled base frequency signal by a fraction frequency coefficient obtained from and proportional to the current PWM duty cycle value. The test signal may be multiplexed with the PWM signal to obtain existing tachometer pulses even when the PWM signal is not asserted. The scale frequency coefficient may only need to be programmed once for each fan.

    Abstract translation: 公开了一种用于产生用于测量计算机系统中的诸如风扇之类的旋转装置的速度的测试信号的系统和方法。 脉宽调制(PWM)信号可以以控制风扇速度的PWM信号的占空比为风扇供电。 风扇可能会产生用于监控风扇转速的转速计脉冲。 测试信号的频率可以被选择为至少两倍于转速计脉冲的频率。 可以使用两个级联分频器从基频信号产生测试信号。 第一分频器可以输出通过将基频信号除以用于与风扇的最大测试信号频率相对应的用户可编程标度频率系数而获得的缩放基频信号。 第二分频器可以通过将经缩放的基本频率信号除以从当前PWM占空比值获得的分数频率系数并与其成比例地输出测试信号。 即使PWM信号未被置位,测试信号也可以与PWM信号进行多路复用以获得现有的转速计脉冲。 每个风扇只需要编程一次规模频率系数。

    Autofan combination of zones
    104.
    发明授权
    Autofan combination of zones 有权
    自动组合区域

    公开(公告)号:US07064511B2

    公开(公告)日:2006-06-20

    申请号:US10759796

    申请日:2004-01-16

    CPC classification number: G05D23/1919

    Abstract: A system and method for controlling a fan is disclosed. A single control signal value for controlling the fan, such as a single PWM duty cycle value for a corresponding PWM generator output powering the fan, may be calculated by combining sensor data from two or more temperature zones. In one embodiment, the single PWM duty cycle value may be determined based on the temperature in a first zone, for example the CPU, with an additional factor based on the temperature in a second zone, for example the ambient temperature of a PC enclosure. In one embodiment, the final single PWM value is determined by adding an offset value to a PWM value calculated based on the current temperature of the first zone, where the offset value is obtained by calculating a first ΔPWM factor for the first zone, and using the first ΔPWM factor, in conjunction with a scaling factor, to weight a second ΔPWM factor calculated for the second zone.

    Abstract translation: 公开了一种用于控制风扇的系统和方法。 可以通过组合来自两个或多个温度区域的传感器数据来计算用于控制风扇的单个控制信号值,例如用于为风扇供电的相应PWM发生器输出的单个PWM占空比值。 在一个实施例中,单个PWM占空比值可以基于第一区域(例如CPU)中的温度,基于第二区域中的温度,例如PC外壳的环境温度,以附加因子来确定。 在一个实施例中,通过将偏移值与基于第一区域的当前温度计算的PWM值相加来确定最终单个PWM值,其中通过计算第一区域的第一DeltaPWM因子获得偏移值,并且使用 第一个DeltaPWM因子结合缩放因子来加权为第二个区域计算的第二个DeltaPWM因子。

    Amplifier with accurate built-in threshold
    105.
    发明授权
    Amplifier with accurate built-in threshold 有权
    放大器具有精确的内置阈值

    公开(公告)号:US07057444B2

    公开(公告)日:2006-06-06

    申请号:US10667535

    申请日:2003-09-22

    Inventor: Paul F. Illegems

    CPC classification number: G05F1/46

    Abstract: Various embodiments of a voltage level detector implemented as an integrated circuit whose trip point is approximately constant over variations in temperature as well as variations in transistor fabrication parameters are disclosed along with a differential amplifier whose input offset voltage is highly immune to said variations. In one embodiment, a voltage generator supplies a composite voltage to the gate of the tail current transistor of the voltage level detector or differential amplifier. The first component of the voltage is approximately equal to the threshold voltage of NMOS transistors comprised in the device over variations in operating temperature as well as variations in transistor fabrication parameters while the second component is approximately constant with respect to said variations. When applied to the gate of the tail current transistor, the first component may turn the transistor on in spite of the above-mentioned parametric variations.

    Abstract translation: 公开了实现为集成电路的电压电平检测器的各种实施例,其跳变点在温度变化上近似恒定,以及晶体管制造参数的变化,以及其输入失调电压对所述变化高度免疫的差分放大器。 在一个实施例中,电压发生器向电压电平检测器或差分放大器的尾电流晶体管的栅极提供复合电压。 电压的第一分量近似等于器件中包含的NMOS晶体管的工作温度变化的阈值电压以及晶体管制造参数的变化,而第二分量相对于所述变化大致恒定。 当施加到尾电流晶体管的栅极时,尽管上述参数变化,第一分量可以使晶体管导通。

    FSK modulator using IQ up-mixers and sinewave coded DACs
    106.
    发明授权
    FSK modulator using IQ up-mixers and sinewave coded DACs 有权
    FSK调制器使用IQ上变频器和正弦波编码DAC

    公开(公告)号:US07043222B2

    公开(公告)日:2006-05-09

    申请号:US10653322

    申请日:2003-09-02

    CPC classification number: H04L27/12

    Abstract: A radio transmitter system designed using an FSK modulator with IQ up-mixers and sinewave coded digital-to-analog converters (DACs). The radio transmitter system may include a frequency shift keying (FSK) coding logic circuit coupled to the inputs of an IQ modulation and image reject up-mixer through a respective DAC and a respective low pass filter (LPF) for each the I and the Q channels. The FSK modulation scheme may employ sine and cosine signals for the I and Q channels, respectively, where the sine and cosine waves are directly coded into the DACs. The coded levels required by the DACs may be generated using current sources and may be Gray-coded. The output of the IQ modulation and image reject up-mixer may be connected to a power amplifier, which may be used to transmit the modulated RF signal via a loop antenna.

    Abstract translation: 无线电发射机系统使用具有IQ上变频器和正弦波编码的数模转换器(DAC)的FSK调制器设计。 无线电发射机系统可以包括频移键控(FSK)编码逻辑电路,其通过相应的DAC和针对I和Q的每个的相应的低通滤波器(LPF)耦合到IQ调制和图像拒绝上混频器的输入 频道 FSK调制方案可以分别将正弦和余弦信号用于I和Q通道,其中正弦和余弦波被直接编码到DAC中。 DAC所需的编码电平可以使用电流源生成,并且可以是灰色编码的。 IQ调制和图像拒绝上混频器的输出可以连接到功率放大器,功率放大器可以用于经由环形天线发送经调制的RF信号。

    Hardware supported peripheral component memory alignment method
    107.
    发明申请
    Hardware supported peripheral component memory alignment method 有权
    硬件支持外设组件内存对齐方式

    公开(公告)号:US20060095611A1

    公开(公告)日:2006-05-04

    申请号:US10979924

    申请日:2004-11-02

    CPC classification number: G06F13/28

    Abstract: A memory alignment system for efficient data transfer between a host system and a remote system comprises a data communications controller configured to align transmitted and received data based on formatting information received from the host system. When transmitting data from local system memory, for example over an Ethernet connection, communications control driver software may first write formatting information corresponding to the data into a configurable transmit data buffer. The data communications controller is operable to align the data based on the formatting information as the driver software moves the data into the transmit data buffer. Similarly, the driver software may write formatting information for receive data into a receive-format configuration buffer. The data communications controller may align the receive data based on the receive-formatting information as the receive data is being written into a configurable receive buffer. As the data communications controller performs all the required data alignment, no data alignment by the host processor is required.

    Abstract translation: 用于在主机系统和远程系统之间有效数据传输的存储器对准系统包括数据通信控制器,其被配置为基于从主机系统接收的格式化信息对准发送和接收的数据。 当通过以太网连接从本地系统存储器发送数据时,通信控制驱动器软件可以首先将对应于数据的格式化信息写入可配置的发送数据缓冲器。 当驱动器软件将数据移动到发送数据缓冲器中时,数据通信控制器可操作以基于格式化信息对准数据。 类似地,驱动软件可以将用于接收数据的格式化信息写入接收格式配置缓冲器。 当接收数据被写入可配置的接收缓冲器时,数据通信控制器可以基于接收格式化信息对准接收数据。 由于数据通信控制器执行所有必需的数据对齐,因此不需要主处理器进行数据对齐。

    Programmable ideality factor compensation in temperature sensors

    公开(公告)号:US20060093016A1

    公开(公告)日:2006-05-04

    申请号:US10979437

    申请日:2004-11-02

    CPC classification number: G01K1/028 G01K7/01

    Abstract: A temperature sensor circuit and system providing accurate readings using a temperature diode whose ideality factor may fall within a determined range. In one set of embodiments a change in diode junction voltage (ΔVBE) proportional to the temperature of the diode is captured and provided to an ADC, which may perform required signal conditioning functions on ΔVBE, and provide a numeric value output corresponding to the temperature of the diode. Errors in the measured temperature that might result from using diodes with ideality factors that differ from an expected ideality factor may be eliminated by programming the system to account for differing ideality factors. The gain of the temperature sensor may be matched to the ideality factor of the temperature diode by using an accurate, highly temperature stable reference voltage of the ADC to set the gain of the temperature measurement system. The reference voltage may have a trim capability to change the gain setting voltage by a digital address comprising a determined number of bits, with the programmable range for the reference voltage corresponding to a determined range of ideality factors.

    METHOD AND CIRCUIT FOR FUSE PROGRAMMING AND ENDPOINT DETECTION
    109.
    发明申请
    METHOD AND CIRCUIT FOR FUSE PROGRAMMING AND ENDPOINT DETECTION 有权
    用于保险丝编程和端点检测的方法和电路

    公开(公告)号:US20050270085A1

    公开(公告)日:2005-12-08

    申请号:US10862675

    申请日:2004-06-07

    Applicant: Paul Illegems

    Inventor: Paul Illegems

    CPC classification number: G11C17/16 G11C17/18

    Abstract: In one embodiment, a system comprises a programming unit coupled to at least one programmable fuse and configured to program the programmable fuse. In addition, the system comprises a monitoring circuit coupled to the programmable fuse and configured to monitor electrical characteristics associated with the programmable fuse while the programmable fuse is being programmed. In one embodiment, the monitoring circuit is configured to detect a voltage associated with the programmable fuse. Furthermore, the monitoring circuit is configured to compare the detected voltage associated with the programmable fuse with a predetermined voltage value (i.e., endpoint detection). If the detected voltage is equal to or less than the predetermined voltage value, the monitoring circuit is configured to change a state of a control signal to stop the programming of the programmable fuse. Otherwise, the programming unit continues to program the programmable fuse.

    Abstract translation: 在一个实施例中,系统包括耦合到至少一个可编程熔丝并被配置为对可编程熔丝进行编程的编程单元。 此外,该系统包括耦合到可编程熔丝的监控电路,并且被配置为在编程可编程熔丝的同时监视与可编程熔丝相关联的电特性。 在一个实施例中,监视电路被配置为检测与可编程保险丝相关联的电压。 此外,监视电路被配置为将与可编程熔丝相关联的检测电压与预定电压值(即端点检测)进行比较。 如果检测到的电压等于或小于预定电压值,则监视电路被配置为改变控制信号的状态以停止可编程熔丝的编程。 否则,编程单元继续编程可编程保险丝。

    Portable RAM drive
    110.
    发明授权
    Portable RAM drive 有权
    便携式RAM驱动器

    公开(公告)号:US06920527B2

    公开(公告)日:2005-07-19

    申请号:US10364583

    申请日:2003-02-11

    CPC classification number: G06F3/0656 G06F3/061 G06F3/0619 G06F3/068

    Abstract: A portable RAM drive comprising data stored on a non-volatile memory and transferable to a volatile memory when the portable RAM drive is coupled to a computer system. When the portable RAM drive is plugged into the computer system, the data from the non-volatile memory may be transferred to the volatile memory for faster access by the computer. If the portable RAM drive is unplugged from the computer, an internal power source may power the portable RAM drive long enough to transfer the data from the volatile memory to the non-volatile memory. In one embodiment, the portable RAM drive may use a restraining device or an indicator light to indicate to the user that the portable RAM drive should not be unplugged from the computer because the data has not yet been transferred from the volatile memory to the non-volatile memory.

    Abstract translation: 一种便携式RAM驱动器,包括存储在非易失性存储器上的数据,并且当便携式RAM驱动器耦合到计算机系统时可转移到易失性存储器。 当便携式RAM驱动器插入计算机系统时,来自非易失性存储器的数据可以被传送到易失性存储器,以便计算机更快地访问。 如果便携式RAM驱动器从计算机拔下,内部电源可以为便携式RAM驱动器供电足够长的时间,以将数据从易失性存储器传输到非易失性存储器。 在一个实施例中,便携式RAM驱动器可以使用约束装置或指示灯来向用户指示便携式RAM驱动器不应该从计算机拔出,因为数据尚未从易失性存储器转移到非易失性存储器, 易失性存储器

Patent Agency Ranking